Parallel algorithms for geometric searching problems
Proceedings of the 1989 ACM/IEEE conference on Supercomputing
The simulation and evaluation of dynamic voltage scaling algorithms
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Cost reduction and evaluation of temporary faults detecting technique
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Total System Energy Minimization for Wireless Image Transmission
Journal of VLSI Signal Processing Systems - Special issue on multimedia signal processing
Soft digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Defect and Error Tolerance in the Presence of Massive Numbers of Defects
IEEE Design & Test
Reliable low-power digital signal processing via reduced precision redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Deployment of Better Than Worst-Case Design: Solutions and Needs
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Fundamentals of wireless communication
Fundamentals of wireless communication
The Design of Error Checkers for Self-Checking Residue Number Arithmetic
IEEE Transactions on Computers
Trends in energy-efficiency and robustness using stochastic sensor network-on-a-chip
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Error-resilient motion estimation architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Stochastic networked computation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-Power Filtering Via Minimum Power Soft Error Cancellation
IEEE Transactions on Signal Processing
IEEE Transactions on Circuits and Systems for Video Technology
Inexact computing using probabilistic circuits: Ultra low-power digital processing
ACM Journal on Emerging Technologies in Computing Systems (JETC)
| Hi-index | 35.68 |
Traditional integrated circuit design achieves error-free operation by designing with margins (clock frequency and supply voltage) and/or including hardware replication and recomputation, which may counter the full energy and area benefits of aggressive technology scaling. It is thus desirable that modern systems-on-chip (SoCs) permit hardware errors while maintaining robust system-level performance. Treating hardware errors as computational noise and extending traditional estimation theory to include practical SoC design constraints yields a novel and general design optimization framework. This work demonstrates the breadth of applicability of the estimation-theoretic framework for system design by showcasing two different application classes that demonstrate 36% to 50% power reduction.