Modeling the wiring of deep submicron ICs
IEEE Spectrum
Transient-fault recovery using simultaneous multithreading
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Latch Design for Transient Pulse Tolerance
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Designing Self-Checking FPGAs through Error Detection Codes
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
A Simplified Gate-Level Fault Model for Crosstalk Effects Analysis
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
A 32-Bit Risc Processor with Concurrent Error Detection
EUROMICRO '98 Proceedings of the 24th Conference on EUROMICRO - Volume 1
Custom S/390 G5 and G6 microprocessors
IBM Journal of Research and Development
Proceedings of the 31st annual international symposium on Computer architecture
Concurrent Error Detection in Wavelet Lifting Transforms
IEEE Transactions on Computers
Going beyond TMR for protection against multiple faults
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
The TTA's Approach to Resilience after Transient Upsets
Real-Time Systems
Software-Based Transparent and Comprehensive Control-Flow Error Detection
Proceedings of the International Symposium on Code Generation and Optimization
Dynamic binary control-flow errors detection
ACM SIGARCH Computer Architecture News - Special issue on the 2005 workshop on binary instrumentation and application
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Configurable isolation: building high availability systems with commodity multi-core processors
Proceedings of the 34th annual international symposium on Computer architecture
Mechanisms for bounding vulnerabilities of processor structures
Proceedings of the 34th annual international symposium on Computer architecture
Compiler-Managed Software-based Redundant Multi-Threading for Transient Fault Detection
Proceedings of the International Symposium on Code Generation and Optimization
Reliability-aware Co-synthesis for Embedded Systems
Journal of VLSI Signal Processing Systems
Study of the Effects of SEU-Induced Faults on a Pipeline Protected Microprocessor
IEEE Transactions on Computers
Probabilistic decision diagrams for exact probabilistic analysis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Adapting to intermittent faults in multicore systems
Proceedings of the 13th international conference on Architectural support for programming languages and operating systems
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Guiding circuit level fault-tolerance design with statistical methods
Proceedings of the conference on Design, automation and test in Europe
Synthesis of fault-tolerant embedded systems
Proceedings of the conference on Design, automation and test in Europe
Analysis of forward error correction methods for nanoscale networks-on-chip
Proceedings of the 2nd international conference on Nano-Networks
Reliability of single-electron logic gates
MINO'07 Proceedings of the 6th conference on Microelectronics, nanoelectronics, optoelectronics
Mixed-mode multicore reliability
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
Improving error tolerance for multithreaded register files
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic heterogeneity and the need for multicore virtualization
ACM SIGOPS Operating Systems Review
Fault emulation for dependability evaluation of VLSI systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Adaptive stochastic routing in fault-tolerant on-chip networks
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Towards scalable reliability frameworks for error prone CMPs
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On hamming product codes with type-II hybrid ARQ for on-chip interconnects
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Selective replication: A lightweight technique for soft errors
ACM Transactions on Computer Systems (TOCS)
From a federated to an integrated automotive architecture
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Metastability-Free Multi-synchronous Communication Scheme for SoCs
SSS '09 Proceedings of the 11th International Symposium on Stabilization, Safety, and Security of Distributed Systems
Counting in the Presence of Memory Faults
ISAAC '09 Proceedings of the 20th International Symposium on Algorithms and Computation
A pulse-density modulation circuit exhibiting noise shaping with single-electron neurons
IJCNN'09 Proceedings of the 2009 international joint conference on Neural Networks
Rapid design space exploration using legacy design data and technology scaling trend
Integration, the VLSI Journal
What von Neumann did not say about multiplexing beyond gate failures: the gory details
IWANN'07 Proceedings of the 9th international work conference on Artificial neural networks
Optimal resilient dynamic dictionaries
ESA'07 Proceedings of the 15th annual European conference on Algorithms
A flexible parallel simulator for networks-on-chip with error control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Transient and Permanent Error Co-management Method for Reliable Networks-on-Chip
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Computation as estimation: a general framework for robustness and energy efficiency in SoCs
IEEE Transactions on Signal Processing
IVF: characterizing the vulnerability of microprocessor structures to intermittent faults
Proceedings of the Conference on Design, Automation and Test in Europe
Hardware/software optimization of error detection implementation for real-time embedded systems
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
OE+IOE: a novel turn model based fault tolerant routing scheme for networks-on-chip
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Proceedings of the Third International Workshop on Network on Chip Architectures
Review: A survey of memory error correcting techniques for improved reliability
Journal of Network and Computer Applications
An autonomous fault tolerant system for CAN communications
IEA/AIE'10 Proceedings of the 23rd international conference on Industrial engineering and other applications of applied intelligent systems - Volume Part III
On the design and analysis of fault tolerant NoC architecture using spare routers
Proceedings of the 16th Asia and South Pacific Design Automation Conference
A resilient on-chip router design through data path salvaging
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Energy/reliability trade-offs in fault-tolerant event-triggered distributed embedded systems
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Cycles, cells and platters: an empirical analysisof hardware failures on a million consumer PCs
Proceedings of the sixth conference on Computer systems
Combined architecture and hardening techniques exploration for reliable embedded system design
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
A (fault-tolerant)2 scheduler for real-time HW tasks
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
A framework for correction of multi-bit soft errors in L2 caches based on redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance optimization of error detection based on speculative reconfiguration
Proceedings of the 48th Design Automation Conference
A self-checking hardware journal for a fault-tolerant processor architecture
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
Fault-tolerant algorithms for tick-generation in asynchronous logic: robust pulse generation
SSS'11 Proceedings of the 13th international conference on Stabilization, safety, and security of distributed systems
On pedagogy of nanometric circuit reliability
The Journal of Supercomputing
Resilient microring resonator based photonic networks
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Resilient algorithms and data structures
CIAC'10 Proceedings of the 7th international conference on Algorithms and Complexity
Networks on chips: structure and design methodologies
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
Fault Resilient Real-Time Design for NoC Architectures
ICCPS '12 Proceedings of the 2012 IEEE/ACM Third International Conference on Cyber-Physical Systems
ACM Transactions on Embedded Computing Systems (TECS)
An efficient routing methodology to tolerate static and dynamic faults in 2-D mesh networks-on-chip
Microprocessors & Microsystems
A study of DRAM failures in the field
SC '12 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
Priority queues resilient to memory faults
WADS'07 Proceedings of the 10th international conference on Algorithms and Data Structures
Accurate and efficient reliability estimation techniques during ADL-driven embedded processor design
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
AVF-driven parity optimization for MBU protection of in-core memory arrays
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
IVF: characterizing the vulnerability of microprocessor structures to intermittent faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Feng shui of supercomputer memory: positional effects in DRAM and SRAM faults
SC '13 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
A fault tolerant NoC architecture using quad-spare mesh topology and dynamic reconfiguration
Journal of Systems Architecture: the EUROMICRO Journal
Journal of Electronic Testing: Theory and Applications
Methods for fault tolerance in networks-on-chip
ACM Computing Surveys (CSUR)
Energy-aware task mapping and scheduling for reliable embedded computing systems
ACM Transactions on Embedded Computing Systems (TECS) - Special Section ESFH'12, ESTIMedia'11 and Regular Papers
Aging-aware hardware-software task partitioning for reliable reconfigurable multiprocessor systems
Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
Communication and migration energy aware task mapping for reliable multiprocessor systems
Future Generation Computer Systems
International Journal of Computer Applications in Technology
Journal of Computer and System Sciences
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Deep-submicron technology is having a significant impact on permanent, intermittent, and transient classes of faults. This article discusses the main trends and challenges in circuit reliability, and explains evolving techniques for dealing with them.