Comparison of Physical and Software-Implemented Fault Injection Techniques
IEEE Transactions on Computers
Fault-tolerant platforms for automotive safety-critical applications
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
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Nanometer Design: What are the Requirements for Manufacturing Test?
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Soft Delay Error Effects in CMOS Combinational Circuits
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
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Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor
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Simulating Single Event Transients in VDSM ICs for Ground Level Radiation
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Concurrent Error Detection in Wavelet Lifting Transforms
IEEE Transactions on Computers
Fingerprinting: bounding soft-error detection latency and bandwidth
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Reliable low-power digital signal processing via reduced precision redundancy
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reflections on Industry Trends and Experimental Research in Dependability
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Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes
IEEE Transactions on Dependable and Secure Computing
A Case for Clumsy Packet Processors
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Efficient Resource Sharing in Concurrent Error Detecting Superscalar Microarchitectures
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Soft error rate estimation and mitigation for SRAM-based FPGAs
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
SWIFT: Software Implemented Fault Tolerance
Proceedings of the international symposium on Code generation and optimization
Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits
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An Accurate SER Estimation Method Based on Propagation Probability
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Increasing Register File Immunity to Transient Errors
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Reliability-Centric High-Level Synthesis
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Gate-Level Mitigation Techniques for Neutron-Induced Soft Error Rate
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
An ILP Formulation for Reliability-Oriented High-Level Synthesis
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Analysis and design of soft-error hardened latches
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Opportunistic Transient-Fault Detection
Proceedings of the 32nd annual international symposium on Computer Architecture
Dynamic Verification of Sequential Consistency
Proceedings of the 32nd annual international symposium on Computer Architecture
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Single event transients in combinatorial circuits
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Toward a multiple clock/voltage island design style for power-aware processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploiting Coarse-Grain Verification Parallelism for Power-Efficient Fault Tolerance
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques
Design and analysis of an NoC architecture from performance, reliability and energy perspective
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
A Soft Error Monitor Using Switching Current Detection
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Replication Cache: A Small Fully Associative Cache to Improve Data Cache Reliability
IEEE Transactions on Computers
Fault Tolerance Techniques for the Merrimac Streaming Supercomputer
SC '05 Proceedings of the 2005 ACM/IEEE conference on Supercomputing
The effects of energy management on reliability in real-time embedded systems
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Cost-effective radiation hardening technique for combinational logic
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A soft error rate analysis (SERA) methodology
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Software-controlled fault tolerance
ACM Transactions on Architecture and Code Optimization (TACO)
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ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Self-stabilizing operating systems
Proceedings of the twentieth ACM symposium on Operating systems principles
Software-Based Transparent and Comprehensive Control-Flow Error Detection
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ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Dynamic binary control-flow errors detection
ACM SIGARCH Computer Architecture News - Special issue on the 2005 workshop on binary instrumentation and application
A dependability perspective on emerging technologies
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Self-Stabilizing Microprocessor: Analyzing and Overcoming Soft Errors
IEEE Transactions on Computers
Soft delay error analysis in logic circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
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Test set enrichment using a probabilistic fault model and the theory of output deviations
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A family of cells to reduce the soft-error-rate in ternary-CAM
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Energy-efficient soft error-tolerant digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Static typing for a faulty lambda calculus
Proceedings of the eleventh ACM SIGPLAN international conference on Functional programming
SlicK: slice-based locality exploitation for efficient redundant multithreading
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
IEEE Transactions on Computers
Reunion: Complexity-Effective Multicore Redundancy
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Architecting a reliable CMP switch architecture
ACM Transactions on Architecture and Code Optimization (TACO)
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Soft error derating computation in sequential circuits
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Soft error reduction in combinational logic using gate resizing and flipflop selection
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Configurable isolation: building high availability systems with commodity multi-core processors
Proceedings of the 34th annual international symposium on Computer architecture
Mechanisms for bounding vulnerabilities of processor structures
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Dynamic prediction of architectural vulnerability from microarchitectural state
Proceedings of the 34th annual international symposium on Computer architecture
Fault-tolerant typed assembly language
Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation
Compiler-Managed Software-based Redundant Multi-Threading for Transient Fault Detection
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Modeling and improving data cache reliability: 1
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Towards Nanoelectronics Processor Architectures
Journal of Electronic Testing: Theory and Applications
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ACM Journal on Emerging Technologies in Computing Systems (JETC)
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Soft error rate analysis for sequential circuits
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 20th annual conference on Integrated circuits and systems design
Zyzzyva: speculative byzantine fault tolerance
Proceedings of twenty-first ACM SIGOPS symposium on Operating systems principles
Probabilistic transfer matrices in symbolic reliability analysis of logic circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Tracking Uncertainty with Probabilistic Logic Circuit Testing
IEEE Design & Test
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Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Adapting to intermittent faults in multicore systems
Proceedings of the 13th international conference on Architectural support for programming languages and operating systems
A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit Technique
Journal of Electronic Testing: Theory and Applications
Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger
Journal of Electronic Testing: Theory and Applications
Soft error rate reduction using redundancy addition and removal
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Soft error vulnerability of iterative linear algebra methods
Proceedings of the 22nd annual international conference on Supercomputing
Analytical techniques for soft error rate modeling and mitigation of FPGA-based designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Online Estimation of Architectural Vulnerability Factor for Soft Errors
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
A fast, analytical estimator for the SEU-induced pulse width in combinational designs
Proceedings of the 45th annual Design Automation Conference
On the role of timing masking in reliable logic circuit design
Proceedings of the 45th annual Design Automation Conference
Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power
Proceedings of the 13th international symposium on Low power electronics and design
Proceedings of the 13th international symposium on Low power electronics and design
Guiding circuit level fault-tolerance design with statistical methods
Proceedings of the conference on Design, automation and test in Europe
A low-cost concurrent error detection technique for processor control logic
Proceedings of the conference on Design, automation and test in Europe
Mitigating Soft Errors in SRAM Address Decoders Using Built-in Current Sensors
Journal of Electronic Testing: Theory and Applications
Reasoning about Control Flow in the Presence of Transient Faults
SAS '08 Proceedings of the 15th international symposium on Static Analysis
Techniques for Efficient Software Checking
Languages and Compilers for Parallel Computing
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Scalable and reliable communication for hardware transactional memory
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
Datapath error detection with no detection latency for high-performance microprocessors
WSEAS Transactions on Computers
Enhancement of fault injection techniques based on the modification of VHDL code
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Intelligent robustness insertion for optimal transient error tolerance improvement in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dependability assessment of by-wire control systems using fault injection
Journal of Systems Architecture: the EUROMICRO Journal
Mixed-mode multicore reliability
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
Process variability-aware transient fault modeling and analysis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Efficient analytical determination of the SEU-induced pulse shape
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Datapath error detection using hybrid detection approach for high-performance microprocessors
ICCOMP'08 Proceedings of the 12th WSEAS international conference on Computers
A new family of sequential elements with built-in soft error tolerance for dual-VDD systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
LADIS '08 Proceedings of the 2nd Workshop on Large-Scale Distributed Systems and Middleware
Reducing the costs of large-scale BFT replication
LADIS '08 Proceedings of the 2nd Workshop on Large-Scale Distributed Systems and Middleware
Dynamic heterogeneity and the need for multicore virtualization
ACM SIGOPS Operating Systems Review
Compiler-assisted soft error detection under performance and energy constraints in embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Self-stabilization preserving compiler
ACM Transactions on Programming Languages and Systems (TOPLAS)
A hybrid nano-CMOS architecture for defect and fault tolerance
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Instruction-Level Fault Tolerance Configurability
Journal of Signal Processing Systems
Design of a soft-error robust microprocessor
Microelectronics Journal
REPAS: Reliable Execution for Parallel ApplicationS in Tiled-CMPs
Euro-Par '09 Proceedings of the 15th International Euro-Par Conference on Parallel Processing
Architecture Design for Soft Errors
Architecture Design for Soft Errors
Towards scalable reliability frameworks for error prone CMPs
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Computing bounds for fault tolerance using formal techniques
Proceedings of the 46th Annual Design Automation Conference
Improving testability and soft-error resilience through retiming
Proceedings of the 46th Annual Design Automation Conference
Circuit optimization techniques to mitigate the effects of soft errors in combinational logic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Signature-based SER analysis and design of logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An improved soft-error rate measurement technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Selective replication: A lightweight technique for soft errors
ACM Transactions on Computer Systems (TOCS)
Improving cache lifetime reliability at ultra-low voltages
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
On soft error rate analysis of scaled CMOS designs: a statistical perspective
Proceedings of the 2009 International Conference on Computer-Aided Design
Consensus When All Processes May Be Byzantine for Some Time
SSS '09 Proceedings of the 11th International Symposium on Stabilization, Safety, and Security of Distributed Systems
Reliable data path design of VLIW processor cores with comprehensive error-coverage assessment
Microprocessors & Microsystems
Checksum-based probabilistic transient-error compensation for linear digital systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
New Self-Checking Booth Multipliers
International Journal of Applied Mathematics and Computer Science - Selected Problems of Computer Science and Control
Shoestring: probabilistic soft error reliability on the cheap
Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems
Cache vulnerability equations for protecting data in embedded processor caches from soft errors
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
Self-stabilizing device drivers
SSS'06 Proceedings of the 8th international conference on Stabilization, safety, and security of distributed systems
Energy-efficient redundant execution for chip multiprocessors
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Cost aware fault tolerant logic synthesis in presence of soft errors
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Protective redundancy overhead reduction using instruction vulnerability factor
Proceedings of the 7th ACM international conference on Computing frontiers
3D simulation and analysis of the radiation tolerance of voltage scaled digital circuit
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
A radiation tolerant phase locked loop design for digital electronics
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
A compiler-based infrastructure for fault-tolerant co-design
Proceedings of the 13th International Workshop on Software & Compilers for Embedded Systems
Fault tolerance in transform-domain adaptive filters operating with real-valued signals
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Fault-Tolerant Flow Control in On-chip Networks
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
False Error Vulnerability Study of On-line Soft Error Detection Mechanisms
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of asynchronous circuits for high soft error tolerance in deep submicrometer CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling soft errors for data caches and alleviating their effects on data reliability
Microprocessors & Microsystems
Partitioning techniques for partially protected caches in resource-constrained embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Formal modeling and reasoning for reliability analysis
Proceedings of the 47th Design Automation Conference
Replica victim caching to improve cache reliability against transient errors
International Journal of High Performance Systems Architecture
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Fault tolerance design by accurate SER estimation for nano-scale circuits
WSEAS Transactions on Circuits and Systems
IVF: characterizing the vulnerability of microprocessor structures to intermittent faults
Proceedings of the Conference on Design, Automation and Test in Europe
Clock skew scheduling for soft-error-tolerant sequential circuits
Proceedings of the Conference on Design, Automation and Test in Europe
A resilience roadmap: (invited paper)
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Multiplexed redundant execution: a technique for efficient fault tolerance in chip multiprocessors
Proceedings of the Conference on Design, Automation and Test in Europe
Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling
Journal of Systems Architecture: the EUROMICRO Journal
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A unified online fault detection scheme via checking of stability violation
Proceedings of the Conference on Design, Automation and Test in Europe
Analysis and optimization of fault-tolerant embedded systems with hardened processors
Proceedings of the Conference on Design, Automation and Test in Europe
Design as you see FIT: system-level soft error analysis of sequential circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Multiple transient faults in combinational and sequential circuits: a systematic approach
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Reliability-aware dynamic energy management in dependable embedded real-time systems
ACM Transactions on Embedded Computing Systems (TECS)
Analysis of checksum-based execution schemes for pipelined processors
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
A probabilistic Boolean logic for energy efficient circuit and system design
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Mitigating soft errors in SRAM-based FPGAs by decoding configuration bits in switch boxes
Microelectronics Journal
Radiation-induced Soft Errors: A Chip-level Modeling Perspective
Foundations and Trends in Electronic Design Automation
Review: A survey of memory error correcting techniques for improved reliability
Journal of Network and Computer Applications
Fully CMOS-compatible on-chip optical clock distribution and recovery
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A timing-aware probabilistic model for single-event-upset analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and optimization of nanometer CMOS circuits for soft-error tolerance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Circuit-level design approaches for radiation-hard digital electronics
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the exploitation of narrow-width values for improving register file reliability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Matrix codes for reliable and cost efficient memory chips
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Placement for immunity of transient faults in cell-based design of nanometer circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Resilience of mutual exclusion algorithms to transient memory faults
Proceedings of the 30th annual ACM SIGACT-SIGOPS symposium on Principles of distributed computing
Design sensitivity of single event transients in scaled logic circuits
Proceedings of the 48th Design Automation Conference
A self-checking hardware journal for a fault-tolerant processor architecture
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
Designing robust threshold gates against soft errors
Microelectronics Journal
Review: New redundant logic design concept for high noise and low voltage scenarios
Microelectronics Journal
Statistical Soft Error Rate (SSER) Analysis for Scaled CMOS Designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Soft core based embedded systems in critical aerospace applications
Journal of Systems Architecture: the EUROMICRO Journal
Trade-offs in transient fault recovery schemes for redundant multithreaded processors
HiPC'06 Proceedings of the 13th international conference on High Performance Computing
On pedagogy of nanometric circuit reliability
The Journal of Supercomputing
Self-stabilization preserving compiler
SSS'05 Proceedings of the 7th international conference on Self-Stabilizing Systems
Memory management for self-stabilizing operating systems
SSS'05 Proceedings of the 7th international conference on Self-Stabilizing Systems
Low-power soft error hardened latch
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Performance implications of failures in large-scale cluster scheduling
JSSPP'04 Proceedings of the 10th international conference on Job Scheduling Strategies for Parallel Processing
Assuring application-level correctness against soft errors
Proceedings of the International Conference on Computer-Aided Design
Impact of faults in combinational logic of commercial microcontrollers
EDCC'05 Proceedings of the 5th European conference on Dependable Computing
Resource-Driven optimizations for transient-fault detecting superscalar microarchitectures
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Reliability-aware core partitioning in chip multiprocessors
Journal of Systems Architecture: the EUROMICRO Journal
Networks on chips: structure and design methodologies
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
Efficient soft error protection for commodity embedded microprocessors using profile information
Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded Systems
A first-order mechanistic model for architectural vulnerability factor
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Fast online error detection and correction with thread signature calculae
Microprocessors & Microsystems
ACM Transactions on Embedded Computing Systems (TECS)
An efficient test design for CMPs cache coherence realizing MESI protocol
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Thread vulnerability in parallel applications
Journal of Parallel and Distributed Computing
Dynamic transient fault detection and recovery for embedded processor datapaths
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A SAFE approach towards early design space exploration of fault-tolerant multimedia MPSoCs
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Soft error-aware power optimization using gate sizing
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Formal Modeling and Verification of Security Property in Handel C Program
International Journal of Secure Software Engineering
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Reconfigurable Concurrent Error Detection Adaptive to Dynamicity of Power Constraints
Journal of Electronic Testing: Theory and Applications
Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
Low cost control flow protection using abstract control signatures
Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
CEP: Correlated Error Propagation for Hierarchical Soft Error Analysis
Journal of Electronic Testing: Theory and Applications
A Bulk Built-In Voltage Sensor to Detect Physical Location of Single-Event Transients
Journal of Electronic Testing: Theory and Applications
An instruction-level fine-grained recovery approach for soft errors
Proceedings of the 28th Annual ACM Symposium on Applied Computing
Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection
Proceedings of the Conference on Design, Automation and Test in Europe
Leveraging variable function resilience for selective software reliability on unreliable hardware
Proceedings of the Conference on Design, Automation and Test in Europe
A layout-based approach for multiple event transient analysis
Proceedings of the 50th Annual Design Automation Conference
Replicating tag entries for reliability enhancement in cache tag arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IVF: characterizing the vulnerability of microprocessor structures to intermittent faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A low-cost, systematic methodology for soft error robustness of logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SCFIT: a FPGA-based fault injection technique for SEU fault model
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Performance-reliability tradeoff analysis for multithreaded applications
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Journal of Systems Architecture: the EUROMICRO Journal
A Probabilistic Approach to Diagnose SETs in Sequential Circuits
Journal of Electronic Testing: Theory and Applications
Verifying quantitative reliability for programs that execute on unreliable hardware
Proceedings of the 2013 ACM SIGPLAN international conference on Object oriented programming systems languages & applications
Methods for fault tolerance in networks-on-chip
ACM Computing Surveys (CSUR)
Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
ACM Transactions on Embedded Computing Systems (TECS)
An analytical method for reliability aware instruction set extension
The Journal of Supercomputing
An infrastructure for accurate characterization of single-event transients in digital circuits
Microprocessors & Microsystems
A low power-delay-product and robust Isolated-DICE based SEU-tolerant latch circuit design
Microelectronics Journal
A Library-Based Early Soft Error Sensitivity Analysis Technique for SRAM-Based FPGA Design
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.01 |
This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to-end model that enables us to compute the soft error rates (SER) for existing and future microprocessor-style designs. The model captures the effects of two important masking phenomena, electrical masking and latching-window masking, which inhibit soft errors in combinational logic. We quantify the SER due to high-energy neutrons in SRAM cells, latches, and logic circuits for feature sizes from 600nm to 50nm and clock periods from 16 to 6 fan-out-of-4 inverter delays. Our model predicts that the SER per chip of logic circuits will increase nine orders of magnitude from 1992 to 2011 and at that point will be comparable to the SER per chip of unprotected memory elements. Our result emphasizes that computer system designers must address the risks of soft errors in logic circuits for future designs.