Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Soft error modeling and remediation techniques in ASIC designs
Microelectronics Journal
Gate input reconfiguration for combating soft errors in combinational circuits
DSNW '10 Proceedings of the 2010 International Conference on Dependable Systems and Networks Workshops (DSN-W)
Soft Error Rate Analysis for Combinational Logic Using an Accurate Electrical Masking Model
IEEE Transactions on Dependable and Secure Computing
Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hi-index | 0.00 |
In this study, we investigated the impact of pulse quenching effect on the soft error vulnerabilities in combinational circuits. Simulation results illustrate that soft error vulnerabilities could be reduced by 4-16% for the benchmark circuits when the pulse quenching effect is introduced. By adjusting the cell orientations of the quenching cells in the layout, the soft error vulnerabilities could be further reduced. It is suggested that new placement algorithm considering circuit reliability should be designed to reduce the circuit soft error vulnerabilities.