Proceedings of the 18th ACM Great Lakes symposium on VLSI
Proceedings of the 46th Annual Design Automation Conference
Circuit optimization techniques to mitigate the effects of soft errors in combinational logic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Accurate linear model for SET critical charge estimation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Formal modeling and reasoning for reliability analysis
Proceedings of the 47th Design Automation Conference
Soft error modeling and remediation techniques in ASIC designs
Microelectronics Journal
Design as you see FIT: system-level soft error analysis of sequential circuits
Proceedings of the Conference on Design, Automation and Test in Europe
An accurate single event effect digital design flow for reliable system level design
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Soft errors have emerged as an important reliability challenge for nanoscale very large scale integration designs. In this paper, we present a fast and efficient soft error rate (SER) analysis methodology for combinational circuits. We first present a novel parametric waveform model based on the Weibull function to represent particle strikes at individual nodes in the circuit. We then describe the construction of the descriptor object that efficiently captures the correlation between the transient waveforms and their associated rate distribution functions. The proposed algorithm consists of operations to inject, propagate, and merge these descriptors while traversing forward along the gates in a circuit. The parameterized waveforms enable an efficient static approach to calculate the SER of a circuit. We exercise the proposed approach on a wide variety of combinational circuits and observe that our algorithm has linear runtime with the size of the circuit. The runtimes for soft error estimation were observed to be in the order of about 1 s, compared to several minutes or even hours for previously proposed methods