A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults
IEEE Transactions on Computers
Model for Transient Fault Susceptibility of Combinational Circuits
Journal of Electronic Testing: Theory and Applications
Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes
IEEE Transactions on Dependable and Secure Computing
Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
On Transistor Level Gate Sizing for Increased Robustness to Transient Faults
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Cost-effective radiation hardening technique for combinational logic
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Latch Susceptibility to Transient Faults and New Hardening Approach
IEEE Transactions on Computers
CMOS VLSI Design: A Circuits and Systems Perspective
CMOS VLSI Design: A Circuits and Systems Perspective
Gate sizing to radiation harden combinational logic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Soft-Error-Rate-Analysis (SERA) Methodology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we present an accurate linear model for estimating the minimum amount of collected charge due to an energetic particle striking a combinational circuit node that may give rise to a SET with an amplitude larger than the noise margin of the subsequent gates. This charge value will be referred to as SET critical charge (QSET). Our proposed model allows to calculate the QSET of a node as a function of the size of the transistors of the gate driving the node and the fan-out gate(s), with no need for time costly electrical level simulations. This makes our approach suitable to be integrated into a design automation tool for circuit radiation hardening. The proposed model features 96% average accuracy compared to electrical level simulations performed by HSPICE. Additionally, it highlights that QSET has a much stronger dependence on the strength of the gate driving the node, than on the node total capacitance. This property could be considered by robust design techniques in order to improve their effectiveness.