Fast timing simulation of transient faults in digital circuits
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IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Sizing CMOS Circuits for Increased Transient Error Tolerance
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Model for Transient Fault Susceptibility of Combinational Circuits
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IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
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IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
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IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
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Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion
Journal of Electronic Testing: Theory and Applications
Circuit optimization techniques to mitigate the effects of soft errors in combinational logic
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A 11-transistor nanoscale CMOS memory cell for hardening to soft errors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Microelectronics Journal
Low-power soft error hardened latch
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Low-leakage soft error tolerant dual-port SRAM cells for cache memory applications
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Journal of Electronic Testing: Theory and Applications
Low-leakage soft error tolerant port-less configuration memory cells for FPGAs
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A low power-delay-product and robust Isolated-DICE based SEU-tolerant latch circuit design
Microelectronics Journal
High Efficiency Time Redundant Hardened Latch for Reliable Circuit Design
Journal of Electronic Testing: Theory and Applications
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In this paper we analyze the conditions making Transient Faults (TFs) affecting the nodes of conventional latch structures generate output Soft-Errors (SEs). We investigate the susceptibility to TFs of all latch nodes and identify the most critical one(s). We show that, for standard latches using back-to-back inverters for their positive feedback, the internal nodes within their feedback path are the most critical. Such nodes will be hereafter referred to as internal feedback nodes. Based on this analysis, we first propose a low cost hardened latch that, compared to alternative hardened solutions, is able to filter out completely TFs affecting its internal feedback nodes, while presenting a lower susceptibility to TFs on the other internal nodes. This is achieved at the cost of a reduced robustness to TFs affecting the output node. To overcome this possible limitation (especially for systems for high reliability applications), we propose another version of our latch that, at the cost of a small area and power consumption increase compared to our first solution, improves also the robustness of the output node, which can be higher than that of alternative hardened solutions. Additionally, both proposed latches present a comparable or higher robustness of the input node than alternative solutions and provide a lower or comparable power-delay product and area overhead than classical implementations and alternative hardened solutions.