Optimization of scannable latches for low energy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes
IEEE Transactions on Dependable and Secure Computing
Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
Latch Susceptibility to Transient Faults and New Hardening Approach
IEEE Transactions on Computers
Flip-Flop Hardening and Selection for Soft Error and Delay Fault Resilience
DFT '09 Proceedings of the 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Low Overhead Soft Error Mitigation Techniques for High-Performance and Aggressive Designs
IEEE Transactions on Computers
Design and Performance Evaluation of Radiation Hardened Latches for Nanoscale CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In a modern high density VLSI design, with higher operating frequency and technology scaling, small critical charge in circuit nodes significantly increases susceptibility to radiation induced transient faults. In this paper, we propose a high efficiency hardened latch using the undesired delay of Schmitt trigger circuit and a special feedback loop to a comparator to build a low overhead time redundancy scheme. The proposed structure masks internal node transient faults also improves the recovery of the output node by transferring the faulty output in two different paths to the comparison circuit's inputs. Experimental results, simulated in 45聽nm CMOS technology, show an acceptable increase in the critical charge compared with the previous hardened latches, with a fair increase in power, delay and area. Monte Carlo simulations have also confirmed the proposed latch resistance to the process, voltage and temperature variations.