IBM experiments in soft fails in computer electronics (1978–1994)
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Field testing for cosmic ray soft errors in semiconductor memories
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Soft-error Monte Carlo modeling program, SEMM
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults
IEEE Transactions on Computers
Hierarchical Simulation Approach to Accurate Fault Modeling for System Dependability Evaluation
IEEE Transactions on Software Engineering
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
A Switch-Level Algorithm for Simulation of Transients in Combinational Logic
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Error Control Coding, Second Edition
Error Control Coding, Second Edition
A static RAM says goodbye to data errors
IEEE Spectrum
Fault Tolerance Design in JPEG 2000 Image Compression System
IEEE Transactions on Dependable and Secure Computing
Logic soft errors in sub-65nm technologies design and CAD challenges
Proceedings of the 42nd annual Design Automation Conference
A Soft Error Monitor Using Switching Current Detection
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
ReStore: Symptom-Based Soft Error Detection in Microprocessors
IEEE Transactions on Dependable and Secure Computing
Exploiting soft redundancy for error-resilient on-chip memory design
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Modeling and improving data cache reliability: 1
Proceedings of the 2007 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Towards Nanoelectronics Processor Architectures
Journal of Electronic Testing: Theory and Applications
Latch Susceptibility to Transient Faults and New Hardening Approach
IEEE Transactions on Computers
Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger
Journal of Electronic Testing: Theory and Applications
Dependability, power, and performance trade-off on a multicore processor
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Online Estimation of Architectural Vulnerability Factor for Soft Errors
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Developing Data Warehouse for Simulation Experiments
RSEISP '07 Proceedings of the international conference on Rough Sets and Intelligent Systems Paradigms
A Systematic Approach to Automatically Generate Multiple Semantically Equivalent Program Versions
Ada-Europe '08 Proceedings of the 13th Ada-Europe international conference on Reliable Software Technologies
Techniques for Efficient Software Checking
Languages and Compilers for Parallel Computing
Datapath error detection with no detection latency for high-performance microprocessors
WSEAS Transactions on Computers
Improving error tolerance for multithreaded register files
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Adopting the Drowsy Technique for Instruction Caches: A Soft Error Perspective
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
The effect of design parameters on single-event upset sensitivity of MOS current mode logic
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Fault emulation for dependability evaluation of VLSI systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture Design for Soft Errors
Architecture Design for Soft Errors
Proceedings of the 46th Annual Design Automation Conference
Reliable data path design of VLIW processor cores with comprehensive error-coverage assessment
Microprocessors & Microsystems
Exploiting memory soft redundancy for joint improvement of error tolerance and access efficiency
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Accurate linear model for SET critical charge estimation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An analytical model for soft error critical charge of nanometric SRAMs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis of single-event effects in embedded processors for non-uniform fault tolerant design
IIT'09 Proceedings of the 6th international conference on Innovations in information technology
Modeling soft errors for data caches and alleviating their effects on data reliability
Microprocessors & Microsystems
System-level hardware-based protection of memories against soft-errors
Proceedings of the Conference on Design, Automation and Test in Europe
Fault effects analysis and reporting system for dependability evaluation
RSCTC'10 Proceedings of the 7th international conference on Rough sets and current trends in computing
Analysis of checksum-based execution schemes for pipelined processors
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Construction of SEU tolerant flip-flops allowing enhanced scan delay fault testing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A timing-aware probabilistic model for single-event-upset analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fault-Tolerant VLIW processor design and error coverage analysis
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
A comparative cost/security analysis of fault attack countermeasures
FDTC'06 Proceedings of the Third international conference on Fault Diagnosis and Tolerance in Cryptography
Reduced-precision redundancy on FPGAs
International Journal of Reconfigurable Computing
A multilevel fault model for integrated parallel fault-tolerant systems
Concurrency and Computation: Practice & Experience
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
IVF: characterizing the vulnerability of microprocessor structures to intermittent faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A low-cost, systematic methodology for soft error robustness of logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
Journal of Electronic Testing: Theory and Applications
An infrastructure for accurate characterization of single-event transients in digital circuits
Microprocessors & Microsystems
Journal of Computer and System Sciences
High Efficiency Time Redundant Hardened Latch for Reliable Circuit Design
Journal of Electronic Testing: Theory and Applications
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Radiation-induced single event upsets (SEUs) pose a major challenge for the design of memories and logic circuits in high-performance microprocessors in technologies beyond 90nm. Historically, we have considered power-performance-area trade offs. There is a need to include the soft error rate (SER) as another design parameter. In this paper, we present radiation particle interactions with silicon, charge collection effects, soft errors, and their effect on VLSI circuits. We also discuss the impact of SEUs on system reliability. We describe an accelerated measurement of SERs using a high-intensity neutron beam, the characterization of SERs in sequential logic cells, and technology scaling trends. Finally, some directions for future research are given.