DEPEND: A Simulation-Based Environment for System Level Dependability Analysis
IEEE Transactions on Computers
ED4I: Error Detection by Diverse Data and Duplicated Instructions
IEEE Transactions on Computers - Special issue on fault-tolerant embedded systems
Detailed design and evaluation of redundant multithreading alternatives
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Dependable Computing and Online Testing in Adaptive and Configurable Systems
IEEE Design & Test
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline
DSN '04 Proceedings of the 2004 International Conference on Dependable Systems and Networks
Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes
IEEE Transactions on Dependable and Secure Computing
A soft error rate analysis (SERA) methodology
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
IBM S/390 parallel enterprise server G5 fault tolerance: a historical perspective
IBM Journal of Research and Development
Logic SER Reduction through Flipflop Redesign
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
An efficient static algorithm for computing the soft error rates of combinational circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Soft error reduction in combinational logic using gate resizing and flipflop selection
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Verification-guided soft error resilience
Proceedings of the conference on Design, automation and test in Europe
Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power
Proceedings of the 13th international symposium on Low power electronics and design
Integration, the VLSI Journal
Single Event crosstalk shielding for CMOS logic
Microelectronics Journal
Circuit optimization techniques to mitigate the effects of soft errors in combinational logic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Placement for immunity of transient faults in cell-based design of nanometer circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The impact of Miller and coupling effects on single event transient in logical circuits
Microelectronics Journal
Single event crosstalk prediction in nanometer technologies
Analog Integrated Circuits and Signal Processing
Soft error-aware power optimization using gate sizing
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Coupling induced soft error mechanisms in nanoscale CMOS technologies
Analog Integrated Circuits and Signal Processing
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Logic soft errors are radiation induced transient errors in sequential elements (flip-flops and latches) and combinational logic. Robust enterprise platforms in sub-65nm technologies require designs with built-in logic soft error protection. Effective logic soft error protection requires solutions to the following three problems: (1) Accurate soft error rate estimation for combinational logic networks; (2) Automated estimation of system effects of logic soft errors, and identification of regions in a design that must be protected; and, (3) New cost-effective techniques for logic soft error protection, because classical fault-tolerance techniques are very expensive.