Gate Sizing to Eliminate Crosstalk Induced Timing Violation
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Logic soft errors in sub-65nm technologies design and CAD challenges
Proceedings of the 42nd annual Design Automation Conference
Effects of Parameter Variations and Crosstalk Noise on H-Tree Clock Distribution Networks
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Capacitive coupling noise in high-speed VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
New Mix codes for multiple bit upsets mitigation in fault-secure memories
Microelectronics Journal
The impact of Miller and coupling effects on single event transient in logical circuits
Microelectronics Journal
Single event crosstalk prediction in nanometer technologies
Analog Integrated Circuits and Signal Processing
Coupling induced soft error mechanisms in nanoscale CMOS technologies
Analog Integrated Circuits and Signal Processing
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With advances in technology scaling, CMOS circuits are increasingly more sensitive to transient pulses caused by Single Event particles. Hardening techniques for CMOS combinational logic have been developed to address the problems associated with Single Event transients, but in these designs, Single Event crosstalk effects have been ignored. In order to complement the Single Event upset (SEU) hardening process, coupling effects among interconnects need to be considered in the Single Event hardening and analysis of CMOS logic gates due to technology scaling effects that increase both SE vulnerability and crosstalk effects. As technologies advance, the coupling effects increasingly cause SE transients to contaminate electronically unrelated circuit paths which can in turn increase the ''Single Event susceptibility'' of CMOS circuits. Serious effects may occur if the affected line is a clock line or an input line of voters in triple-modular redundancy (TMR) circuit. Hence, this work first analyzes Single Event crosstalk on recent technologies and then proposes hardening techniques to reduce Single Event crosstalk. Hardening results are demonstrated using HSpice Simulations with interconnect and device parameters derived in 90nm technology.