Software pioneers: contributions to software engineering
Software pioneers: contributions to software engineering
A multiple bit upset tolerant SRAM memory
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Single Event crosstalk shielding for CMOS logic
Microelectronics Journal
Design of parallel fault-secure encoders for systematic cyclic block transmission codes
Microelectronics Journal
Soft error modeling and remediation techniques in ASIC designs
Microelectronics Journal
Efficient Two-Dimensional Error Codes for Multiple Bit Upsets Mitigation in Memory
DFT '10 Proceedings of the 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems
Fault secure encoder and decoder for nanomemory applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Matrix codes for reliable and cost efficient memory chips
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A system architecture solution for unreliable nanoelectronic devices
IEEE Transactions on Nanotechnology
Majority multiplexing-economical redundant fault-tolerant designs for nanoarchitectures
IEEE Transactions on Nanotechnology
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Nowadays, multibit error correction codes (MECCs) are effective approaches to mitigate multiple bit upsets (MBUs) in memories. As technology scales, combinational circuits have become more susceptible to radiation induced single event transient (SET). Therefore, transient faults in encoding and decoding circuits are more frequent than before. Firstly, this paper proposes a new MECC, which is called Mix code, to mitigate MBUs in fault-secure memories. Considering the structure characteristic of MECC, Euclidean Geometry Low Density Parity Check (EG-LDPC) codes and Hamming codes are combined in the proposed Mix codes to protect memories against MBUs with low redundancy overheads. Then, the fault-secure scheme is presented, which can tolerate transient faults in both the storage cell and the encoding and decoding circuits. The proposed fault-secure scheme has remarkably lower redundancy overheads than the existing fault-secure schemes. Furthermore, the proposed scheme is suitable for ordinary accessed data width (e.g., 2^n bits) between system bus and memory. Finally, the proposed scheme has been implemented in Verilog and validated through a wide set of simulations. The experiment results reveal that the proposed scheme can effectively mitigate multiple errors in whole memory systems. They can not only reduce the redundancy overheads of the storage array but also improve the performance of MECC circuits in fault-secure memory systems.