Theory of Information and Coding
Theory of Information and Coding
Nanowire-based sublithographic programmable logic arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Error Control Coding, Second Edition
Error Control Coding, Second Edition
Nanowire-based programmable architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Fault Secure Encoder and Decoder for Memory Applications
DFT '07 Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Fault tolerant nano-memory with fault secure encoder and decoder
Proceedings of the 2nd international conference on Nano-Networks
Nonphotolithographic nanoscale memory density prospects
IEEE Transactions on Nanotechnology
Deterministic addressing of nanoscale devices assembled at sublithographic pitches
IEEE Transactions on Nanotechnology
Defect and Transient Fault-Tolerant System Design for Hybrid CMOS/Nanodevice Digital Memories
IEEE Transactions on Nanotechnology
Run-Time Data-Dependent Defect Tolerance for Hybrid CMOS/Nanodevice Digital Memories
IEEE Transactions on Nanotechnology
IEEE Transactions on Information Theory - Part 1
Low-density parity-check codes based on finite geometries: a rediscovery and new results
IEEE Transactions on Information Theory
IEEE Transactions on Information Theory
Redundant Residue Number System Code for Fault-Tolerant Hybrid Memories
ACM Journal on Emerging Technologies in Computing Systems (JETC)
New Mix codes for multiple bit upsets mitigation in fault-secure memories
Microelectronics Journal
SEU tolerant robust latch design
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Memory cells have been protected from soft errors for more than a decade; due to the increase in soft error rate in logic circuits, the encoder and decoder circuitry around the memory blocks have become susceptible to soft errors as well and must also be protected. We introduce a new approach to design fault-secure encoder and decoder circuitry for memory designs. The key novel contribution of this paper is identifying and defining a new class of error-correcting codes whose redundancy makes the design of fault-secure detectors (FSD) particularly simple. We further quantify the importance of protecting encoder and decoder circuitry against transient errors, illustrating a scenario where the system failure rate (FIT) is dominated by the failure rate of the encoder and decoder. We prove that Euclidean Geometry Low-Density Parity-Check (EG-LDPC) codes have the fault-secure detector capability. Using some of the smaller EG-LDPC codes, we can tolerate bit or nanowire defect rates of 10% and fault rates of 10-18 upsets/device/cycle, achieving a FIT rate at or below one for the entire memory system and a memory density of 1011 bit/cm2 with nanowire pitch of 10 nm for memory blocks of 10 Mb or larger. Larger EG-LDPC codes can achieve even higher reliability and lower area overhead.