Error Control Coding, Second Edition
Error Control Coding, Second Edition
Fault Secure Encoder and Decoder for Memory Applications
DFT '07 Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Fault secure encoder and decoder for nanomemory applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Information Theory
Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In a recent paper, a method was proposed to accelerate the majority logic decoding of difference set low density parity check codes. This is useful as majority logic decoding can be implemented serially with simple hardware but requires a large decoding time. For memory applications, this increases the memory access time. The method detects whether a word has errors in the first iterations of majority logic decoding, and when there are no errors the decoding ends without completing the rest of the iterations. Since most words in a memory will be error-free, the average decoding time is greatly reduced. In this brief, we study the application of a similar technique to a class of Euclidean geometry low density parity check (EG-LDPC) codes that are one step majority logic decodable. The results obtained show that the method is also effective for EG-LDPC codes. Extensive simulation results are given to accurately estimate the probability of error detection for different code sizes and numbers of errors.