Cell architecture for nanoelectronic design
Microelectronics Journal
Nanowire addressing with randomized-contact decoders
Theoretical Computer Science
Fault tolerant nano-memory with fault secure encoder and decoder
Proceedings of the 2nd international conference on Nano-Networks
Stochastic nanoscale addressing for logic
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Fault secure encoder and decoder for nanomemory applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Multiple techniques have now been proposed using random addressing to build demultiplexers which interface between the large pitch of lithographically patterned features and the smaller pitch of self-assembled sublithographic nanowires. At the same time, the relatively high defect rates expected for molecular-sized devices and wires dictate that we design architectures with spare components so we can map around defective elements. To accommodate and mask both of these effects, we introduce a programmable addressing scheme which can be used to provide deterministic addresses for decoders built with random nanoscale addressing and potentially defective wires. We describe how this programmable addressing scheme can be implemented with emerging, nanoscale building blocks and show how to build deterministically addressable memory banks. We characterize the area required for this programmable addressing scheme. For 2048×2048 memory banks, the area overhead for address correction is less than 33%, delivering net memory densities around 1011 b/cm2.