Information Theory, Inference & Learning Algorithms
Information Theory, Inference & Learning Algorithms
Probability and Computing: Randomized Algorithms and Probabilistic Analysis
Probability and Computing: Randomized Algorithms and Probabilistic Analysis
Evaluation of design strategies for stochastically assembled nanoarray memories
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Nanowire-based programmable architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Radial addressing of nanowires
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Analysis of Mask-Based Nanowire Decoders
IEEE Transactions on Computers
Nanowire addressing with randomized-contact decoders
Theoretical Computer Science
Reliable computing at the nanoscale
Reliable computing at the nanoscale
Deterministic addressing of nanoscale devices assembled at sublithographic pitches
IEEE Transactions on Nanotechnology
Assembling nanoscale circuits with randomized connections
IEEE Transactions on Nanotechnology
Deterministic nanowire fanout and interconnect without any critical translational alignment
IEEE Transactions on Nanotechnology
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In this paper we explore the area overhead associated with the stochastic assembly of nanoscale logic. In nanoscale architectures, stochastically assembled nanowire decoders have been proposed as a way of addressing many individual nanowires using as few photolithographically produced mesoscale wires as possible. Previous work has bounded the area of stochastically assembled nanowire decoders for controlling nanowire crossbar-based memories. We extend this analysis to nanowire crossbar-based logic and bound the area required to supply inputs to a nanoscale circuit via mesoscale wires. We also relate our analysis to the area required for stochastically assembled signal-restoration layers within nanowire crossbar-based logic.