PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
FPGA routing architecture: segmentation and buffering to optimize speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
HSRA: high-speed, hierarchical synchronous reconfigurable array
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Bounding Fan-out in Logical Networks
Journal of the ACM (JACM)
NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Introduction to VLSI Systems
Minimizing FPGA Interconnect Delays
IEEE Design & Test
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Reconfigurable Architectures for General-Purpose Computing
Reconfigurable Architectures for General-Purpose Computing
Nanowire-based sublithographic programmable logic arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Design of programmable interconnect for sublithographic programmable logic arrays
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Seven Strategies for Tolerating Highly Defective Fabrication
IEEE Design & Test
Law of large numbers system design
Nano, quantum and molecular computing
Array-based architecture for FET-based, nanoscale electronics
IEEE Transactions on Nanotechnology
Stochastic assembly of sublithographic nanoscale interfaces
IEEE Transactions on Nanotechnology
Nonphotolithographic nanoscale memory density prospects
IEEE Transactions on Nanotechnology
Structures and electrical properties of Ag-tetracyanoquinodimethane organometallic nanowires
IEEE Transactions on Nanotechnology
Channel width and length dependence in Si nanocrystal memories with ultra-nanoscale channel
IEEE Transactions on Nanotechnology
Performance-driven mapping for CPLD architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new hybrid FPGA with nanoscale clusters and CMOS routing
Proceedings of the 43rd annual Design Automation Conference
Nanowire addressing with randomized-contact decoders
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Towards Nanoelectronics Processor Architectures
Journal of Electronic Testing: Theory and Applications
Evaluating area and performance of hybrid FPGAs with nanoscale clusters and CMOS routing
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Modeling self-developing biological neural networks
Neurocomputing
Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
The amorphous FPGA architecture
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
The synthesis of robust polynomial arithmetic with stochastic logic
Proceedings of the 45th annual Design Automation Conference
Logic synthesis with nanowire crossbar: reality check and standard cell-based integration
Proceedings of the conference on Design, automation and test in Europe
An efficient test and characterization approach for nanowire-based architectures
Proceedings of the 21st annual symposium on Integrated circuits and system design
FPGA Architecture: Survey and Challenges
Foundations and Trends in Electronic Design Automation
Nanowire addressing with randomized-contact decoders
Theoretical Computer Science
Fault tolerant nano-memory with fault secure encoder and decoder
Proceedings of the 2nd international conference on Nano-Networks
Towards achieving reliable and high-performance nanocomputing via dynamic redundancy allocation
ACM Journal on Emerging Technologies in Computing Systems (JETC)
FPCNA: a field programmable carbon nanotube array
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Towards a framework for designing applications onto hybrid nano/CMOS fabrics
Microelectronics Journal
Hybrid nanoelectronics: future of computer technology
Journal of Computer Science and Technology
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
A hybrid nano-CMOS architecture for defect and fault tolerance
ACM Journal on Emerging Technologies in Computing Systems (JETC)
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A defect/error-tolerant nanosystem architecture for DSP
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Nanoscale digital computation through percolation
Proceedings of the 46th Annual Design Automation Conference
Design and evaluation of a carbon nanotube-based programmable architecture
International Journal of Parallel Programming
Nanowire crossbar logic and standard cell-based integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
NanoV: nanowire-based VLSI design
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Stochastic nanoscale addressing for logic
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Reconfigurable circuit design with nanomaterials
Proceedings of the Conference on Design, Automation and Test in Europe
Runtime analysis for defect-tolerant logic mapping on nanoscale crossbar architectures
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
Variation-aware logic mapping for crossbar nano-architectures
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Fault secure encoder and decoder for nanomemory applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variation-immune quasi delay-insensitive implementation on nano-crossbar arrays
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Automatic abstraction and fault tolerance in cortical microachitectures
Proceedings of the 38th annual international symposium on Computer architecture
Defect-Aware Nanocrossbar Logic Mapping through Matrix Canonization Using Two-Dimensional Radix Sort
ACM Journal on Emerging Technologies in Computing Systems (JETC)
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
Graphene nanoribbon crossbar nanomesh
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
Nanofabric power analysis: Biosequence alignment case study
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
A Reconfigurable PLA Architecture for Nanomagnet Logic
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Proceedings of the International Conference on Computer-Aided Design
Reliable logic mapping on Nano-PLA architectures
Proceedings of the great lakes symposium on VLSI
Hybrid Redundancy for Defect Tolerance in Molecular Crossbar Memory
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Fault-tolerant programmable logic array for nanoelectronics
International Journal of Circuit Theory and Applications
Defect-tolerant logic hardening for crossbar-based nanosystems
Proceedings of the Conference on Design, Automation and Test in Europe
ILP formulations for variation/defect-tolerant logic mapping on crossbar nano-architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A Hardware Viewpoint on Biosequence Analysis: What’s Next?
ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special Issue on Bioinformatics
Nanoarray architectures multilevel simulation
ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special Issue on Reliability and Device Degradation in Emerging Technologies and Special Issue on WoSAR 2011
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Chemists can now construct wires which are just a few atoms in diameter; these wires can be selectively field-effect gated, and wire crossings can act as diodes with programmable resistance. These new capabilities present both opportunities and challenges for constructing nanoscale computing systems. The tiny feature sizes offer a path to economically scale down to atomic dimensions. However, the associated bottom-up synthesis techniques only produce highly regular structures and come with high defect rates and minimal control during assembly. To exploit these technologies, we develop nanowire-based architectures which can bridge between lithographic and atomic-scale feature sizes and tolerate defective and stochastic assembly of regular arrays to deliver high density universal computing devices. Using 10nm pitch nanowires, these nanowire-based programmable architectures offer one to two orders of magnitude greater mapped-logic density than defect-free lithographic FPGAs at 22nm.