Performance-driven mapping for CPLD architectures
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Molecular electronics: devices, systems and tools for gigagate, gigabit chips
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Nanowire-based programmable architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Defect-tolerant Logic with Nanoscale Crossbar Circuits
Journal of Electronic Testing: Theory and Applications
Variation-aware logic mapping for crossbar nano-architectures
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Variation-immune quasi delay-insensitive implementation on nano-crossbar arrays
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Single-walled carbon nanotube electronics
IEEE Transactions on Nanotechnology
Stochastic assembly of sublithographic nanoscale interfaces
IEEE Transactions on Nanotechnology
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Emerging molecular based nanoelectronics is a promising alternatives for current CMOS technology to reduce manufacturing costs and achieve higher levels of integration. Extreme parameter variations resulted from nondeterministic nanofabrication can seriously affect the correct functionality and performance of circuits implemented in this technology. In this paper, we introduce modifications to nano-PLA, a major nano-architecture, to immune it against extreme variations by using self-timed local control signaling within the blocks instead of external global signals. Extensive Monte Carlo simulations for delay variations on a set of benchmarks confirms that the circuits implemented on the proposed architecture are 100% immune against delay variation, compared to only 37% for those circuits implemented on the original nano-PLA architecture. Moreover, the proposed architecture results in 47% reduction, in average, in critical path delay of mapped circuits.