Graphical evolution: an introduction to the theory of random graphs
Graphical evolution: an introduction to the theory of random graphs
NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Seven Strategies for Tolerating Highly Defective Fabrication
IEEE Design & Test
CAEN-BIST: Testing the NanoFabric
ITC '04 Proceedings of the International Test Conference on International Test Conference
SCT: An Approach For Testing and Configuring Nanoscale Devices
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Nano, quantum and molecular computing: implications to high level design and validation
Nano, quantum and molecular computing: implications to high level design and validation
Array-based architecture for FET-based, nanoscale electronics
IEEE Transactions on Nanotechnology
Stochastic assembly of sublithographic nanoscale interfaces
IEEE Transactions on Nanotechnology
Nonphotolithographic nanoscale memory density prospects
IEEE Transactions on Nanotechnology
Defect-tolerant adder circuits with nanoscale crossbars
IEEE Transactions on Nanotechnology
Assembling nanoscale circuits with randomized connections
IEEE Transactions on Nanotechnology
A study of asynchronous design methodology for robust CMOS-nano hybrid system design
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Runtime analysis for defect-tolerant logic mapping on nanoscale crossbar architectures
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
Proceedings of the International Conference on Computer-Aided Design
Defect-tolerant logic hardening for crossbar-based nanosystems
Proceedings of the Conference on Design, Automation and Test in Europe
ILP formulations for variation/defect-tolerant logic mapping on crossbar nano-architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Crossbar architectures are one approach to molecular electronic circuits for memory and logic applications. However, currently feasible manufacturing technologies for molecular electronics introduce numerous defects so insisting on defect-free crossbars would give unacceptably low yields. Instead, increasing the area of the crossbar provides enough redundancy to implement circuits in spite of the defects. We identify reliability thresholds in the ability of defective crossbars to implement boolean logic. These thresholds vary among different implementations of the same logical formula, allowing molecular circuit designers to trade-off reliability, circuit area, crossbar geometry and the computational complexity of locating functional components. We illustrate these choices for binary adders. For instance, one adder implementation yields functioning circuits 90% of the time with 30% defective crossbar junctions using an area only 1.8 times larger than the minimum required for a defect-free crossbar. We also describe an algorithm for locating a combination of functional junctions that can implement an adder circuit in a defective crossbar.