Defect-tolerant Logic with Nanoscale Crossbar Circuits
Journal of Electronic Testing: Theory and Applications
Built-in Self-test and Defect Tolerance in Molecular Electronics-based Nanofabrics
Journal of Electronic Testing: Theory and Applications
BISM: built-in self map for hybrid crossbar nano-architectures
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Low-overhead defect tolerance in crossbar nanoarchitectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
ILP formulations for variation/defect-tolerant logic mapping on crossbar nano-architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Molecular electronics-based devices are assumed to include at least 10^10 gate-equivalents/cm2 and defect densities as high as 10%; novel test strategies are necessary to efficiently test and diagnose these nanoscale devices. Configuration time, test time and defect map size are among the major challenges for these new devices. In this paper, we propose a new approach that simultaneously configures and tests nano devices. A new built-in self-test (BIST) scheme for testing and defect tolerance of nanoscale devices is proposed. The proposed procedure is based on testing reconfigurable nanoblocks at the time of implementing a function of a desired application on that block. This simultaneous configuration and test (SCT) procedure considerably reduces the test and configuration time. It also eliminates the need for storing the location of the defects in the defect map on/off-chip. The presented probabilistic analyses results show the effectiveness of this process in terms of test and configuration time for architectures with rich interconnect resources.