NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Molecular electronics: devices, systems and tools for gigagate, gigabit chips
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
BIST-Based Detection and Diagnosis of Multiple Faults in FPGAs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
On the Defect Tolerance of Nano-Scale Two-Dimensional Crossbars
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
Defect and Fault Tolerance of Reconfigurable Molecular Computing
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Built-In Self-Test of Molecular Electronics-Based Nanofabrics
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
CAEN-BIST: Testing the NanoFabric
ITC '04 Proceedings of the International Test Conference on International Test Conference
Application-Dependent Diagnosis of FPGAs
ITC '04 Proceedings of the International Test Conference on International Test Conference
SCT: An Approach For Testing and Configuring Nanoscale Devices
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Application-dependent testing of FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Array-based architecture for FET-based, nanoscale electronics
IEEE Transactions on Nanotechnology
Stochastic assembly of sublithographic nanoscale interfaces
IEEE Transactions on Nanotechnology
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In hybrid nano architectures, self-assembled nanoscale crossbars are fabricated on top a reliable CMOS subsystem. Bottom-up selfassembly process used in the fabrication of nanoscale devices yields significantly more defects compared to the conventional top-down lithography used in CMOS fabrication. Therefore, applying defect tolerant design schemes is inevitable in order to map the design to these programmable fabrics by bypassing defects. In this paper, we present an alternative approach for defect tolerant mapping in which the mapping phase is built into the programmable fabric and reliable on-chip resources are used for on-the-fly defectfree mapping. This built-in self map (BISM) scheme significantly reduces the complexity of defect tolerance during design time as well as post-fabrication configuration time. Various BISMschemes are presented and their efficiencies in terms of defect tolerance and mapping time are compared.