SCT: A novel approach for testing and configuring nanoscale devices
ACM Journal on Emerging Technologies in Computing Systems (JETC)
BISM: built-in self map for hybrid crossbar nano-architectures
Proceedings of the 19th ACM Great Lakes symposium on VLSI
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Fine grain faults diagnosis of FPGA interconnect
Microprocessors & Microsystems
Memory block based scan-BIST architecture for application-dependent FPGA testing
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
| Hi-index | 0.00 |
A new technique for diagnosis of faults in the interconnects and logic blocks of an arbitrary design implemented on an FPGA is presented. This work is complementary to application-dependent detection methods for FPGAs. This technique can uniquely identify any single bridging, open, or stuck-at fault in the interconnect as well as any single functional fault in the logic blocks. The number of test configurations for interconnect diagnosis is logarithmic to the size of the mapped design, whereas logic diagnosis is performed in only one test configuration.