Diagnosing programmable interconnect systems for FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Interconnect testing in cluster-based FPGA architectures
Proceedings of the 37th Annual Design Automation Conference
Diagnosis of interconnect faults in cluster-based FPGA architectures
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Built-in self-test of FPGA interconnect
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A Diagnosis Method for Interconnects in SRAM Based FPGAs
ATS '98 Proceedings of the 7th Asian Test Symposium
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
On the diagnosis of programmable interconnect systems: Theory and application
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
BIST-Based Detection and Diagnosis of Multiple Faults in FPGAs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
BIST-Based Diagnosis of FPGA Interconnect
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Diagnosis of interconnects and FPICs using a structured walking-1 approach
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Application-Dependent Testing of FPGA Interconnects
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
A Multi-Configuration Strategy for an Application Dependent Testing of FPGAs
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Application-Dependent Diagnosis of FPGAs
ITC '04 Proceedings of the International Test Conference on International Test Conference
Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free Assumptions
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Application-dependent testing of FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High Resolution Application Specific Fault Diagnosis of FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper proposes a new fine grain fault diagnosis method for the interconnect of an arbitrary design implemented in a Field Programmable Gate Array (FPGA). In the proposed method, interconnect faults detected at the primary output are back-tracked until the faulty nets are precisely located. This is carried out by programming the LUTs on the faulty path to be transparent and thus propagating the value of a specific net under test to the primary output for verification against the expected value of the net. After every back-tracking iteration, the fault location is narrowed down and thus the number of nets to be tested decreases significantly. Therefore, the upper bound of the number of configurations (N"M"A"X) required to locate a faulty net, depends on the maximum combinational depth (D"C"O"M"B) of the circuit, and it is approximately equivalent to three times of D"C"O"M"B. The proposed method has the ability to locate multiple faults without any fault masking with fault coverage that includes all possible stuck-at, open and pair-wise bridging faults. The proposed method is validated on the ISCAS'89 benchmark circuits mapped on Xilinx Spartan 3E, Virtex-4 and Virtex-5 FPGAs and the results are presented. The simulation results show that applying the proposed method on circuits with less combinational depth reduces the required number of test configurations on average by 35% when compared with the latest method available in the literature.