Field-programmable gate arrays
Field-programmable gate arrays
Bridging fault detection in FPGA interconnects using IDDQ
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Testing configurable LUT-based FPGA's
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-line fault detection for bus-based field programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Tolerating operational faults in cluster-based FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Testing the Interconnect of RAM-Based FPGAs
IEEE Design & Test
Using ILA Testing for BIST in FPGAs
Proceedings of the IEEE International Test Conference on Test and Design Validity
BIST-Based Diagnostics of FPGA Logic Blocks
Proceedings of the IEEE International Test Conference
Built-in self-test of FPGA interconnect
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Detection of bridging faults in logic resources of configurable FPGAs using I_DDQ
ITC '98 Proceedings of the 1998 IEEE International Test Conference
SRAM-based FPGA's: testing the LUT/RAM modules
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Using Roving STARs for On-Line Testing and Diagnosis of FPGAs in Fault-Tolerant Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
FPGA test time reduction through a novel interconnect testing scheme
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Using embedded FPGAs for SoC yield improvement
Proceedings of the 39th annual Design Automation Conference
Diagnosis of interconnect faults in cluster-based FPGA architectures
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
BIST-Based Detection and Diagnosis of Multiple Faults in FPGAs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
BIST-Based Delay Path Testing in FPGA Architectures
ITC '01 Proceedings of the 2001 IEEE International Test Conference
BIST-Based Delay-Fault Testing in FPGAs
Journal of Electronic Testing: Theory and Applications
FPGA Bridging Fault Detection and Location via Differential I{DDQ}
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Application-Specific Bridging Fault Testing of FPGAs
Journal of Electronic Testing: Theory and Applications
Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs
Journal of Electronic Testing: Theory and Applications
An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs
Journal of Electronic Testing: Theory and Applications
Fault tolerance of switch blocks and switch block arrays in FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Application-dependent testing of FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fine grain faults diagnosis of FPGA interconnect
Microprocessors & Microsystems
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As IC densities are increasing, cluster-based FPGA architectures are becoming the architecture of choice for major FPGA manufacturers. A cluster-based architecture is one in which several logic blocks are grouped together into a coarse-grained logic block. While the high density local interconnect often found within clusters serves to improve FPGA utilization, it also greatly complicates the FPGA interconnect testing problem. To address this issue, we have developed a hierarchical approach to define a set of FPGA configurations which enable interconnect faults to be detected. This technique enables the detection of bridging faults involving intra-cluster interconnect and extra-cluster interconnect. The hierarchical structure of a cluster-based tile is exploited to define intra-cluster configurations separately from extra-cluster configurations, thereby improving the efficiency of the configuration definition process. By guaranteeing that both intra-cluster and extra-cluster configurations have several test transparency properties, hierarchical fault detectability is ensured.