Testing configurable LUT-based FPGA's
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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ATS '00 Proceedings of the 9th Asian Test Symposium
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ITC '00 Proceedings of the 2000 IEEE International Test Conference
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IOLTW '02 Proceedings of the Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02)
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ITC '99 Proceedings of the 1999 IEEE International Test Conference
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The objective of this paper is to propose a method to test all the delay faults located in Look-Up-Tables (LUTs) of SRAM-based symmetrical FPGAs. This method is developed in a Manufacturing-Oriented Context (MOT). In the first part of the paper, the timing behavior of the LUTs and the physical defects inducing delay faults in the LUTs are analyzed. Then, the detection conditions to test such delay faults are established and requirements on test vectors are derived. Finally a test configuration scheme and its associated test sequence able to test exhaustively the delay faults in all LUTs of a symmetrical FPGA are proposed.