Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Field-programmable gate arrays
Field-programmable gate arrays
Diagnosing programmable interconnect systems for FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Evaluation of FPGA resources for built-in self-test of programmable logic blocks
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Testing the configurable interconnect/logic interface of SRAM-based FPGA's
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Functional Testing of Semiconductor Random Access Memories
ACM Computing Surveys (CSUR)
RAM-based FPGA's: a test approach for the configurable logic
Proceedings of the conference on Design, automation and test in Europe
Field-Programmable Gate Array Technology
Field-Programmable Gate Array Technology
Universal Fault Diagnosis for Lookup Table FPGAs
IEEE Design & Test
Testing the Interconnect of RAM-Based FPGAs
IEEE Design & Test
Testing of programmable logic devices (PLD) with faulty resources
DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
Fault Modeling and Test Generation for FPGAs
FPL '94 Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications
SRAM-based FPGA's: testing the LUT/RAM modules
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Minimizing the Number of Test Configurations for Different FPGA Families
ATS '99 Proceedings of the 8th Asian Test Symposium
Universal test complexity of field-programmable gate arrays
ATS '95 Proceedings of the 4th Asian Test Symposium
A Test Methodology for Interconnect Structures of LUT-based FPGAs
ATS '96 Proceedings of the 5th Asian Test Symposium
Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA
ATS '97 Proceedings of the 6th Asian Test Symposium
Testing for the programming circuit of LUT-based FPGAs
ATS '97 Proceedings of the 6th Asian Test Symposium
Testing memory modules in SRAM-based configurable FPGAs
MTDT '97 Proceedings of the 1997 IEEE International Workshop on Memory Technology, Design and Testing
An approach for testing programmable/configurable field programmable gate arrays
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Test of RAM-based FPGA: methodology and application to the interconnect
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Testing for Faults in Wiring Networks
IEEE Transactions on Computers
On the Set of Target Path Delay Faults in Sequential Subcircuits of LUT-based FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Using satisfiability in application-dependent testing of FPGA interconnects
Proceedings of the 40th annual Design Automation Conference
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
Application-Specific Bridging Fault Testing of FPGAs
Journal of Electronic Testing: Theory and Applications
Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs
Journal of Electronic Testing: Theory and Applications
An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs
Journal of Electronic Testing: Theory and Applications
Test, diagnosis and fault simulation of embedded RAM modules in SRAM-based FPGAs
Microelectronic Engineering
Application-dependent testing of FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we describe an experiment aboutstructural testing of two XILINX FPGAs families. In ourpractical approach, the FPGA is divided into differentarrays: an array of logic cells, an array of interconnectcells and an array of RAM cells. For each part, we use aspecific fault model and we generate test configurationsand test vectors for the considered models. In each case,for each array, we try to minimize as much as possible thenumber of test configurations because re-programmingFPGAs is really time consuming.