Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Field-programmable gate arrays
Field-programmable gate arrays
SRAM-Based FPGAs: Testing the Embedded RAM Modules
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Functional Testing of Semiconductor Random Access Memories
ACM Computing Surveys (CSUR)
RAM-based FPGA's: a test approach for the configurable logic
Proceedings of the conference on Design, automation and test in Europe
Field-Programmable Gate Array Technology
Field-Programmable Gate Array Technology
SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
Fault Modeling and Test Generation for FPGAs
FPL '94 Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications
SRAM-based FPGA's: testing the LUT/RAM modules
ITC '98 Proceedings of the 1998 IEEE International Test Conference
March-based RAM diagnosis algorithms for stuck-at and coupling faults
Proceedings of the IEEE International Test Conference 2001
Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA
ATS '97 Proceedings of the 6th Asian Test Symposium
SRAM-Based FPGA's: Testing the Interconnect/Logic Interface
ATS '98 Proceedings of the 7th Asian Test Symposium
Testing memory modules in SRAM-based configurable FPGAs
MTDT '97 Proceedings of the 1997 IEEE International Workshop on Memory Technology, Design and Testing
An approach for testing programmable/configurable field programmable gate arrays
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Test of RAM-based FPGA: methodology and application to the interconnect
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Different Experiments in Test Generation for XILINX FPGAs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Comments on "An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories"
IEEE Transactions on Computers
An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories
IEEE Transactions on Computers
A March Test for Functional Faults in Semiconductor Random Access Memories
IEEE Transactions on Computers
Hi-index | 2.88 |
This paper presents a unique scheme for testing and locating multiple stuck at faults in the embedded RAM modules of SRAM-based FPGAs. The RAM modules are tested using the MATS++ algorithm. The interconnection scheme makes it possible to test all the cells within the RAM modules in the FPGA in just one test configuration. We also develop a diagnosis scheme capable of locating the faulty RAM cells and the CLB in which it is located. In this research, emphasis is also laid on reducing the testing time, which is achieved by partitioning the FPGA into two halves.