Fault analysis for computer memory systems and combinatorial logic networks
Fault analysis for computer memory systems and combinatorial logic networks
Detection oF Pattern-Sensitive Faults in Random-Access Memories
IEEE Transactions on Computers
An Algorithm for Testing Random Access Memories
IEEE Transactions on Computers
Fault location in memory systems by program
AFIPS '69 (Spring) Proceedings of the May 14-16, 1969, spring joint computer conference
Built-In Testing of Memory Using an On-Chip Compact Testing Scheme
IEEE Transactions on Computers
SRAM-based FPGA's: testing the LUT/RAM modules
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test, diagnosis and fault simulation of embedded RAM modules in SRAM-based FPGAs
Microelectronic Engineering
Testing Memories for Single-Cell Pattern-Sensitive Faults
IEEE Transactions on Computers
Efficient Algorithms for Testing Semiconductor Random-Access Memories
IEEE Transactions on Computers
Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories
IEEE Transactions on Computers
A March Test for Functional Faults in Semiconductor Random Access Memories
IEEE Transactions on Computers
Built-in testing of memory using on-chip compact testing scheme
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
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This correspondence presents an optimal algorithm to detect any single "stuck-at-i," "stuck-at-O" fault and any combination of "stuck-at-I," "stuck-at-O" multiple faults in a random access memory using only the n-bit memory address register input and m-bit memory buffer register input and output lines. It is shown that this algorithm requires 4 X 2n memory accesses.