Computer
Detection oF Pattern-Sensitive Faults in Random-Access Memories
IEEE Transactions on Computers
Testing Memories for Single-Cell Pattern-Sensitive Faults
IEEE Transactions on Computers
Fault Location in a Semiconductor Random-Access Memory Unit
IEEE Transactions on Computers
Efficient Algorithms for Testing Semiconductor Random-Access Memories
IEEE Transactions on Computers
Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories
IEEE Transactions on Computers
An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories
IEEE Transactions on Computers
A Graph Model for Pattern-Sensitive Faults in Random Access Memories
IEEE Transactions on Computers
Test generation for VLSI chips with embedded memories
IBM Journal of Research and Development
A RAM Architecture for Concurrent Access and on Chip Testing
IEEE Transactions on Computers
Partitioning algorithm to enhance VLSI testability
ACM-SE 36 Proceedings of the 36th annual Southeast regional conference
Symmetric transparent BIST for RAMs
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Self-adjusting output data compression: an efficient BIST technique for RAMs
Proceedings of the conference on Design, automation and test in Europe
IEEE Design & Test
A Tutorial on Built-In Self-Test, Part 2: Applications
IEEE Design & Test
Efficient Online and Offline Testing of Embedded DRAMs
IEEE Transactions on Computers
Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
Unified scan design with scannable memory arrays
ATS '95 Proceedings of the 4th Asian Test Symposium
Error Detecting Refreshment for Embedded DRAMs
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Nondestructive RAM Testing by Analyzing the Output Data for Symmetry
Automation and Remote Control
Efficient O(√n ) BIST algorithms for DDNPS faults in dual port memories
ITC'94 Proceedings of the 1994 international conference on Test
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In this paper we study the problem of testing RAM. A new fault model, which encompasses the existing fault models, is proposed. We then propose a scheme of testing faults from the new fault model using built-in testing techniques. We introduce concept of p-hard and determine the complexity of the extra hardware required for built-in self-testing on our hardness scale. A novel approach using microcoded ROM for implementation of built-in testing is also proposed and its complexity is determined.