Built-In Testing of Memory Using an On-Chip Compact Testing Scheme
IEEE Transactions on Computers
IEEE Design & Test
Serial Interfacing for Embedded-Memory Testing
IEEE Design & Test
Delay Test: The Next Frontier for LSSD Test Systems
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Test Features of the HP PA7100LC Processor
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Testabilty Features of the MC 68060 Microprocessor
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Balancing Structured and Ad-hoc Design for Test: Testing of the PowerPC 603TM Microprocessor
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Test generation systems in Japan
DAC '75 Proceedings of the 12th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
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Scan design has been popular as a design-for-testability technique. A memory array, however, has been considered non-scannable. This paper describes unified scan design that makes a memory array scannable and allows mixing of memory arrays and ordinary flip-flops in a single scan path. Based on a rule that considers ordinary flip-flops as a memory array with one word, the existing CAD system can generate the test pattern automatically without making any distinction between flip-flops and memory arrays. A long scan path involving a number of memory arrays can be split into multiple scan paths to reduce scan operation time.