Model generation of test logic for macrocell based designs
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Delay Fault Coverage Enhancement Using Variable Observation Times
Journal of Electronic Testing: Theory and Applications
Debug Facilities in the TriMedia CPU64 Architecture
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Test Development for Second-Generation ColdFire Microprocessors
IEEE Design & Test
Pentium Pro Processor Design for Test and Debug
IEEE Design & Test
Design for Debug: Catching Design Errors in Digital Chips
IEEE Design & Test
The Superscalar Architecture of the MC68060
IEEE Micro
Unified scan design with scannable memory arrays
ATS '95 Proceedings of the 4th Asian Test Symposium
Using ATPG for clock rules checking in complex scan designs
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
A Case Study of the Test Development for the 2nd Generation ColdFire® Microprocessors
ITC '97 Proceedings of the 1997 IEEE International Test Conference
PENTIUM® PRO PROCESSOR DESIGN FOR TEST AND DEBUG
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips
Journal of Electronic Testing: Theory and Applications
AC Scan Path Selection for Physical Debugging
IEEE Design & Test
Cell Broadband Engine Debugging for Unknown Events
IEEE Design & Test
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