Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
microSPARCTM: A Case Study of Scan-Based Debug
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Structured Design-for-Debug - The SuperSPARCTM II Methodology and Implementation
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Pentium® Pro Processor Design for Test and Debug
Proceedings of the IEEE International Test Conference
Testabilty Features of the MC 68060 Microprocessor
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
TriMedia CPU64 Application Development Environment
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Silicon Debug: Scan Chains Alone Are Not Enough
ITC '99 Proceedings of the 1999 IEEE International Test Conference
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This paper describes debug facilities in the PhilipsTriMedia CPU64, which is an embedded processor core for multimediaapplications. Its architecture provides a VLIW pipeline, support for64-bit vector data, and virtual memory management. The debug hardwarein the TriMedia CPU64 supports two complementary debug strategies.One strategy provides a snapshot of the processor state at certainmoments in time, which is achieved by single-step execution andvarious breakpoint types. The other debug strategy providescontinuous monitoring of the processor state by using a PC tracebuffer. Precise exceptions are used to provide accurate contextswitching from application software to debugger software.