Pentium® Pro Processor Design for Test and Debug

An IEEE 1149.1 Compliant Test Control Architecture

Journal of Electronic Testing: Theory and Applications

Debug Facilities in the TriMedia CPU64 Architecture

Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999

Estimating the Economic Benefits of DFT

IEEE Design & Test

Configurations for IDDQ-Testable PLAs

IEEE Design & Test

Design for Debug: Catching Design Errors in Digital Chips

IEEE Design & Test

High volume microprocessor test escapes, an analysis of defects our tests are missing

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Testability access of the high speed test features in the Alpha 21264 microprocessor

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Test Methodology for the McKinley Processor

ITC '01 Proceedings of the 2001 IEEE International Test Conference

DPDAT: DATA PATH DIRECT ACCESS TESTING

ITC '01 Proceedings of the 2001 IEEE International Test Conference

Debug Methodology for the McKinley Processor

ITC '01 Proceedings of the 2001 IEEE International Test Conference

A Study of Bridging Defect Probabilities on a Pentium (tm) 4 CPU

ITC '01 Proceedings of the 2001 IEEE International Test Conference

Design-For-Test Methodology for Motorola PowerPCTM Microprocessors

ITC '99 Proceedings of the 1999 IEEE International Test Conference

IDDQ Testing in Deep Submicron Integrated Circuits

ITC '99 Proceedings of the 1999 IEEE International Test Conference

Silicon Debug: Scan Chains Alone Are Not Enough

ITC '99 Proceedings of the 1999 IEEE International Test Conference

Design for (Physical) Debug for Silicon Microsurgery and Probing of Flip-Chip Packaged Integrated Circuits

ITC '99 Proceedings of the 1999 IEEE International Test Conference

Delay Defect Characteristics and Testing Strategies

IEEE Design & Test

Robust System Design with Built-In Soft-Error Resilience

Computer

A design for failure analysis (DFFA) technique to ensure incorruptible signatures

Proceedings of the conference on Design, automation and test in Europe: Proceedings

An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs

ACM Journal on Emerging Technologies in Computing Systems (JETC)

Sequential element design with built-in soft error resilience

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability

Deterministic test for the reproduction and detection of board-level functional failures

Proceedings of the 16th Asia and South Pacific Design Automation Conference

Tracking on-chip age using distributed, embedded sensors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Gradual diagnostic test generation and observation point insertion based on the structural distance between indistinguished fault pairs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Built-in generation of multicycle functional broadside tests with observation points

ACM Transactions on Design Automation of Electronic Systems (TODAES)