High volume microprocessor test escapes, an analysis of defects our tests are missing

Authors:
Wayne M. Needham;Cheryl Prunty;Yeoh Eng Hong
Affiliations:
-;-;-
Venue:
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Year:
1998

Citing 6
Cited 49

DFT Strategy for Intel Microprocessors

Proceedings of the IEEE International Test Conference on Test and Design Validity
IDDQ and AC Scan: The War Against Unmodelled Defects

Proceedings of the IEEE International Test Conference on Test and Design Validity
So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment

Proceedings of the IEEE International Test Conference
Pentium® Pro Processor Design for Test and Debug

Proceedings of the IEEE International Test Conference
The Application of Novel Failure Analysis Techniques for Advanced Multi-Layered CMOS Devices

Proceedings of the IEEE International Test Conference
An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing

VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium

Test generation for resistive opens in CMOS

Proceedings of the 12th ACM Great Lakes symposium on VLSI
Detectability Conditions of Full Opens in the Interconnections

Journal of Electronic Testing: Theory and Applications
Test and Reliability: Partners in IC Manufacturing, Part 1

IEEE Design & Test
Current-Based Testing for Deep-Submicron VLSIs

IEEE Design & Test
Resistance Characterization for Weak Open Defects

IEEE Design & Test
A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers

Journal of Electronic Testing: Theory and Applications
Effects of Multi-cycle Sensitization on Delay Tests

VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Testing for Tunneling Opens

ITC '00 Proceedings of the 2000 IEEE International Test Conference
An Analysis of the Delay Defect Detection Capability of the ECR Test Method

ITC '00 Proceedings of the 2000 IEEE International Test Conference
Multiple-Parameter CMOS IC Testing with Increased Sensitivity for IDDQ

ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Method Evaluation Experiments & Data

ITC '00 Proceedings of the 2000 IEEE International Test Conference
A BIST Approach for Very Deep Sub-Micron (VDSM) Defects

ITC '00 Proceedings of the 2000 IEEE International Test Conference
Logic Mapping on a Microprocessor

ITC '00 Proceedings of the 2000 IEEE International Test Conference
Rapid-Response Temperature Control Provides New Defect Screening Opportunities

ITC '01 Proceedings of the 2001 IEEE International Test Conference
Testing for Resistive Opens and Stuck Opens

ITC '01 Proceedings of the 2001 IEEE International Test Conference
An Histogram Based Procedure for Current Testing of Active Defects

ITC '99 Proceedings of the 1999 IEEE International Test Conference
High Speed Digital Transceivers: A Challenge For Manufacturing

ITC '99 Proceedings of the 1999 IEEE International Test Conference
A DFT Technique for High Performance Circuit Testing

ITC '99 Proceedings of the 1999 IEEE International Test Conference
Diagnostic Techniques for the IBM S/390 600 MHz G5 Microprocessor

ITC '99 Proceedings of the 1999 IEEE International Test Conference
Towards Reducing "Functional Only" Fails for the UltraSPARCTM Microprocessors

ITC '99 Proceedings of the 1999 IEEE International Test Conference
Defect-Based Delay Testing of Resistive Vias-Contacts A Critical Evaluation

ITC '99 Proceedings of the 1999 IEEE International Test Conference
Testing high-performance pipelined circuits with slow-speed testers

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Detection of Temperature Sensitive Defects Using ZTC

VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
New Test Methodology for Resistive Open Defect Detection in Memory Address Decoders

VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
DFT for Delay Fault Testing of High-Performance Digital Circuits

IEEE Design & Test
Design and analysis of a scheme to mitigate condensation on an assembly used to cool a processor module

IBM Journal of Research and Development
High-end server low-temperature cooling

IBM Journal of Research and Development
Memory Testing Under Different Stress Conditions: An Industrial Evaluation

Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test

Journal of Electronic Testing: Theory and Applications
A new classification of path-delay fault testability in terms of stuck-at faults

Journal of Computer Science and Technology
Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 μm and 90 nm technologies

Proceedings of the 42nd annual Design Automation Conference
Via Distribution Model for Yield Estimation

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Scaling of iDDT Test Methods for Random Logic Circuits

Journal of Electronic Testing: Theory and Applications
Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test generation in the presence of timing exceptions and constraints

Proceedings of the 44th annual Design Automation Conference
Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits

Journal of Electronic Testing: Theory and Applications
Scan Test Response Compaction Combined with Diagnosis Capabilities

Journal of Electronic Testing: Theory and Applications
Defect Analysis and Defect Tolerant Design of Multi-port SRAMs

Journal of Electronic Testing: Theory and Applications
Graphical IDDQ signatures reduce defect level and yield loss

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Small-delay defect detection in the presence of process variations

Microelectronics Journal
A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines

Journal of Electronic Testing: Theory and Applications
S/390 G5 CMOS microprocessor diagnostics

IBM Journal of Research and Development
Multi-temperature testing for core-based system-on-chip

Proceedings of the Conference on Design, Automation and Test in Europe
On-Chip Delay Measurement Based Response Analysis for Timing Characterization

Journal of Electronic Testing: Theory and Applications
Study of Read Recovery Dynamic Faults in 6T SRAMS and Method to Improve Test Time

Journal of Electronic Testing: Theory and Applications
Reliability-enhancement and self-repair schemes for SRAMs with static and dynamic faults

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis of Resistive Open Defects in Drowsy SRAM Cells

Journal of Electronic Testing: Theory and Applications
Impact of resistive-open defects on the heat current of TAS-MRAM architectures

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper explores defects found in a high volumemicroprocessor when shipping at a low defect level. Abrief description of the manufacturing flow along withdefinition of DPM is covered. Three defective devices arethen root cause analyzed for defect type, electrical effectand possible ways to screen earlier in the device life cycleor manufacturing process. The implications of thesedefects along with process trends are used to forecast theneed for better tools and methods to earlier achieve highquality goals.