So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment

Guest Editors' Introduction: Tough Challenges as Design and Test Go Nanometer

Computer

Design for Delay Testability in High-Speed Digital ICs

Journal of Electronic Testing: Theory and Applications

Current-Based Testing for Deep-Submicron VLSIs

IEEE Design & Test

Estimation of defect-free IDDQ in submicron circuits using switch level simulation

ITC '98 Proceedings of the 1998 IEEE International Test Conference

High volume microprocessor test escapes, an analysis of defects our tests are missing

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Toward understanding "Iddq-only" fails

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Defect level prediction for I_DDQ testing

ITC '98 Proceedings of the 1998 IEEE International Test Conference

A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers

Journal of Electronic Testing: Theory and Applications

Replacing IDDQ Testing: With Variance Reduction

Journal of Electronic Testing: Theory and Applications

Bridging the Testing Speed Gap: Design for Delay Testability

ETW '00 Proceedings of the IEEE European Test Workshop

A Novel Method to Improve the Test Efficiency of VLSI Tests

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference

Built-In Current Sensor for IDDQ Testing in Deep Submicron CMOS

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium

Multiple-Parameter CMOS IC Testing with Increased Sensitivity for IDDQ

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Test Method Evaluation Experiments & Data

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Comparing Functional and Structural Tests

ITC '00 Proceedings of the 2000 IEEE International Test Conference

An Empirical Study on the Effects of Test Type Ordering on

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Improving Delta-IDDQ-based test methods

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Improved Wafer-level Spatial Analysis for IDDQ Limit Setting

ITC '01 Proceedings of the 2001 IEEE International Test Conference

APPLICATION AND ANALYSIS OF IDDQ DIAGNOSTIC SOFTWARE

ITC '97 Proceedings of the 1997 IEEE International Test Conference

Intrinsic Leakage in Low Power Deep Submicron CMOS ICs

ITC '97 Proceedings of the 1997 IEEE International Test Conference

Current Signatures: Application

ITC '97 Proceedings of the 1997 IEEE International Test Conference

Current Signatures: Application

ITC '98 Proceedings of the 1998 IEEE International Test Conference

A Comparison of Bridging Fault Simulation Methods

ITC '99 Proceedings of the 1999 IEEE International Test Conference

A Study of Test Quality/Tester Scan Memory Trade-offs Using the SEMATECH Test Methods Data

ITC '99 Proceedings of the 1999 IEEE International Test Conference

An Histogram Based Procedure for Current Testing of Active Defects

ITC '99 Proceedings of the 1999 IEEE International Test Conference

1998 ITC Best Paper: Failure Analysis of Timing and IDDQ-only Failures from the SEMATECH Test Methods Experiment

ITC '99 Proceedings of the 1999 IEEE International Test Conference

A DFT Technique for High Performance Circuit Testing

ITC '99 Proceedings of the 1999 IEEE International Test Conference

Embedded X86 Testing Methodology

ITC '99 Proceedings of the 1999 IEEE International Test Conference

Eliminating the Ouija® Board: Automatic Thresholds and Probabilistic IDDQ Diagnosis

ITC '99 Proceedings of the 1999 IEEE International Test Conference

Defect-Based Delay Testing of Resistive Vias-Contacts A Critical Evaluation

ITC '99 Proceedings of the 1999 IEEE International Test Conference

Testing high-performance pipelined circuits with slow-speed testers

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power

IDDQ data analysis using neighbor current ratios

Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Desing and test of systems on a chip

Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Overcoming post-silicon validation challenges through quick error detection (QED)

Proceedings of the Conference on Design, Automation and Test in Europe