So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment
Proceedings of the IEEE International Test Conference
Application and Analysis of IDDQ Diagnostic Software
Proceedings of the IEEE International Test Conference
Current Signatures: Application
Proceedings of the IEEE International Test Conference
Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Toward understanding "Iddq-only" fails
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Current signatures [VLSI circuit testing]
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
IEEE Design & Test
On Redundancy and Fault Detection in Sequential Circuits
IEEE Transactions on Computers
An Empirical Study on the Effects of Test Type Ordering on
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Optimization Trade-offs for Vector Volume and Test Power
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Case Study on t e Implementation of t e Illinois Scan Architecture
ITC '01 Proceedings of the 2001 IEEE International Test Conference
| Hi-index | 0.00 |
Monolithic ICs are growing so large that tester capacity is rapidly becoming a problem. There are also anumber of "stored pattern" test methods which vie forlimited tester resources. From a quality perspective,how do we best allocate tester memory or time? Inthis paper, I use the SEMATECH Test Methods datato examine this important question.