On the Adaptation of Viterbi Algorithm for Diagnosis of Multiple Bridging Faults
IEEE Transactions on Computers
Diagnosis Method Using ΔIDDQ Probabilistic Signatures: Theory and Results
Journal of Electronic Testing: Theory and Applications
Fault models and test generation for IDDQ testing: embedded tutorial
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
IDDQ Testing: Issues Present and Future
IEEE Design & Test
IC Failure Analysis: Magic, Mystery, and Science
IEEE Design & Test
IC Diagnosis Using Multiple Supply Pad IDDQs
IEEE Design & Test
Estimation of defect-free IDDQ in submicron circuits using switch level simulation
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Toward understanding "Iddq-only" fails
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Diagnosis method based on /spl Delta/Iddq probabilistic signatures: experimental results
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Replacing IDDQ Testing: With Variance Reduction
Journal of Electronic Testing: Theory and Applications
New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
On the Comparison of IDDQ and IDDQ Testing
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Current Ratios: A Self-Scaling Technique for Production IDDQ Testing
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Stuck-Fault Tests vs. Actual Defects
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Method Evaluation Experiments & Data
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Increasing the IDDQ Test Resolution Using Current Prediction
ITC '00 Proceedings of the 2000 IEEE International Test Conference
DECOUPLE: DEFECT CURRENT DETECTION IN DEEP SUBMICRON IDDQ
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Improved Wafer-level Spatial Analysis for IDDQ Limit Setting
ITC '01 Proceedings of the 2001 IEEE International Test Conference
The Future of Delta IDDQ Testing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
An Evaluation of Defect-Oriented Test: WELL-controlled Low Voltage Test
ITC '01 Proceedings of the 2001 IEEE International Test Conference
APPLICATION AND ANALYSIS OF IDDQ DIAGNOSTIC SOFTWARE
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Current Signatures: Application
ITC '97 Proceedings of the 1997 IEEE International Test Conference
SO WHAT IS AN OPTIMAL TEST MIX? A DISCUSSION OF THE SEMATECH METHODS EXPERIMENT
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Current Signatures: Application
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A Study of Test Quality/Tester Scan Memory Trade-offs Using the SEMATECH Test Methods Data
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Clustering Based Techniques for IDDQ Testing
ITC '99 Proceedings of the 1999 IEEE International Test Conference
An Histogram Based Procedure for Current Testing of Active Defects
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Current Ratios: A Self-Scaling Technique for Production IDDQ Testing
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Statistical Threshold Formulation For Dynamic Idd Test
ITC '99 Proceedings of the 1999 IEEE International Test Conference
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
Testing and Reliability Techniques for High-Bandwidth Embedded RAMs
Journal of Electronic Testing: Theory and Applications
On New Current Signatures and Adaptive Test Technique Combination
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
FPGA Bridging Fault Detection and Location via Differential I{DDQ}
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
IDDX-based test methods: A survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Defect Detection Using Quiescent Signal Analysis
Journal of Electronic Testing: Theory and Applications
Quiescent-Signal Analysis: A Multiple Supply Pad IDDQ Method
IEEE Design & Test
Graphical IDDQ signatures reduce defect level and yield loss
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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In this paper we demonstrate that performing I/sub DDQ/ testing against a single threshold current value does not make sense. In place of the single current threshold we propose the "current signature". A die's current signature takes into account the relative measured level of current on all applied I/sub DDQ/ vectors. Preliminary results of current signature applications are discussed as well.