Introduction to statistical pattern recognition (2nd ed.)
Introduction to statistical pattern recognition (2nd ed.)
IDDQ testing as a component of a test suite: the need for several fault coverage metrics
Journal of Electronic Testing: Theory and Applications - Special issue on IDDQ testing of VLSI circuits
Introduction to IDDQ testing
Defect oriented testing for CMOS analog and digital circuits
Defect oriented testing for CMOS analog and digital circuits
Deep submicron defect detection with the energy consumption ratio
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Probability and Statistics with Reliability, Queuing and Computer Science Applications
Probability and Statistics with Reliability, Queuing and Computer Science Applications
Analysis of Application of the IDDQ Technique to the Deep Sub-Micron VLSI Testing
Journal of Electronic Testing: Theory and Applications
Current-Based Testing for Deep-Submicron VLSIs
IEEE Design & Test
The future of delta I_DDQ testing
Proceedings of the IEEE International Test Conference 2001
IDDQ Test: Sensitivity Analysis of Scaling
Proceedings of the IEEE International Test Conference on Test and Design Validity
Towards an Effective IDDQ Test Vector Selection and Application Methodology
Proceedings of the IEEE International Test Conference on Test and Design Validity
Burn-in Elimination of a High Volume Microprocessor Using IDDQ
Proceedings of the IEEE International Test Conference on Test and Design Validity
High volume microprocessor test escapes, an analysis of defects our tests are missing
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing for bridging faults (shorts) in CMOS circuits
DAC '83 Proceedings of the 20th Design Automation Conference
New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Current signatures [VLSI circuit testing]
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
On the Comparison of IDDQ and IDDQ Testing
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Clustering Based Evaluation of IDDQ Measurements: Applications in Testing and Classification of ICs
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
An Analysis of the Delay Defect Detection Capability of the ECR Test Method
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Increasing the IDDQ Test Resolution Using Current Prediction
ITC '00 Proceedings of the 2000 IEEE International Test Conference
DECOUPLE: DEFECT CURRENT DETECTION IN DEEP SUBMICRON IDDQ
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Current Signatures: Application
ITC '98 Proceedings of the 1998 IEEE International Test Conference
IDDQ '97 Proceedings of the 1997 IEEE International Workshop on IDDQ Testing (IDDQ '97)
IDDQ Data Analysis Using Current Signature
IDDQ '98 Proceedings of the IEEE International Workshop on IDDQ Testing
Detection and location of faults and defects using digital signal processing
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Clustering Based Techniques for IDDQ Testing
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Current Ratios: A Self-Scaling Technique for Production IDDQ Testing
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IDDQ Testing in Deep Submicron Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Graphical cmos i(ddq) testing signatures based on data mining
Graphical cmos i(ddq) testing signatures based on data mining
IC test using the energy consumption ratio
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We propose a new IDDQ testing signature, the graphical IDDQ signature. We discovered that noise, in the entire set of current measurements for a chip, is a vastly superior feature for classifying chips as good or bad, compared to present methods. The measured IDDQ current as a function of vectors is defined here as the signature. We examine the shape of the waveform defined by the total set of the IDDQ measurements, to extract the number of bands that all of the current measurements cluster into, the width and separation of the bands and current glitches or noise among all IDDQ measurements. We examined the IDDQ signatures of all SEMATECH experiment chips that were classified as good or bad by a combination of functional, delay, and scan voltage tests. A single IDDQ threshold, whether absolute or differential, cannot separate good/bad chips reliably. Good chip signatures contain discrete levels (or bands) of varying widths and separations. A faulty chip almost always displays noise and glitches in the band structure. The graphical IDDQ classifier shows very high accuracy for SEMATECH test data with a test escape rate of 5.97%, compared with 7.5% for the single threshold method, 7.6% for current differences and 7.5% for the Δ IDDQ method. The graphical IDDQ method had a 1.2% test overkill, compared with 2.3% for the single threshold method, 6.1% for current differences and 7.0% for Δ IDDQ.