New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
On the Comparison of IDDQ and IDDQ Testing
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
The Future of Delta IDDQ Testing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
IDDX-based test methods: A survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Graphical IDDQ signatures reduce defect level and yield loss
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The goals of this paper are (1) to improve the effectiveness of IDDQ testing, and (2) to find the characteristic current signature for every defect class. Current signature analysis was performed for the IDDQ data collected on the Murphy test chip. A "total variance" method is proposed to reduce the test escape of IDDQ testing. Compared to the other three IDDQ testing methods, it has the lowest test escape and the highest yield loss. However, there are still 7.5% non-functional CUTs which could not be detected by any IDDQ testing method. This result shows that it is not possible to replace Boolean tests by IDDQ testing. The distributions of six current signature types over six different classes are analyzed. The results show that "big-step" is the dominant signature type among all defect classes.