Introduction to IDDQ testing
Current-Based Testing for Deep-Submicron VLSIs
IEEE Design & Test
Burn-in Elimination of a High Volume Microprocessor Using IDDQ
Proceedings of the IEEE International Test Conference on Test and Design Validity
Screening for Known Good Die (KGD) Based on Defect Clustering: An Experimental Study
Proceedings of the IEEE International Test Conference
Current signatures [VLSI circuit testing]
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
The Future of Delta IDDQ Testing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Current Signatures for Production Testing
IDDQ '96 Proceedings of the 1996 IEEE International Workshop on IDDQ Testing (IDDQ '96)
IDDQ Data Analysis Using Current Signature
IDDQ '98 Proceedings of the IEEE International Workshop on IDDQ Testing
Current Ratios: A Self-Scaling Technique for Production IDDQ Testing
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Graphical IDDQ signatures reduce defect level and yield loss
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
The measured IDDQ current as a function of vectors isdefined here as the IDDQ signature of a chip. We examinedthe IDDQ signatures of a large number of SEMATECHchips that have been classified us good or bud by a combineddecision from functional, delay and scan tests. We findthat a single IDDQ threshold, whether absolute or differential, cannot separate good/bud chips with any desirableaccuracy, because the good chip signature can be any oneof several well-defined graphs. In general, the signature ofa good chip is found to contain discrete levels (or bands)of varying widths and separations. A faulty chip almostalways displays noise and glitches in the band structure.Bused on observations, we develop a set of five graphicalcriteria, which provide lower defect level and yield losscompared to other non-IDDQ test methods. The reason isthat the graphical procedure customizes the decision for thechip-under-test, and may substantially reduce the usage ofother conventional tests.