A logic chip delay-test method based on system timing
IBM Journal of Research and Development
An Experimental Chip to Evaluate Test Techniques: Chip and Experiment Design
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
An Experimental Chip to Evaluate Test Techniques: Experiment Results
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Analysis and Detection of Timing Failures in an Experimental Test Chip
Proceedings of the IEEE International Test Conference on Test and Design Validity
IDDQ and AC Scan: The War Against Unmodelled Defects
Proceedings of the IEEE International Test Conference on Test and Design Validity
Delay Test: The Next Frontier for LSSD Test Systems
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A Comparison of Defect Models for Fault Location with IDDQ Measurements
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Testing for bridging faults (shorts) in CMOS circuits
DAC '83 Proceedings of the 20th Design Automation Conference
Universal fault simulation using fault tuples
Proceedings of the 37th Annual Design Automation Conference
Reducing the complexity of defect level modeling using the clustering effect
DATE '00 Proceedings of the conference on Design, automation and test in Europe
On the Adaptation of Viterbi Algorithm for Diagnosis of Multiple Bridging Faults
IEEE Transactions on Computers
Diagnosis Method Using ΔIDDQ Probabilistic Signatures: Theory and Results
Journal of Electronic Testing: Theory and Applications
Proceedings of the 38th annual Design Automation Conference
Studies of the SEMATECH IDDq test data
Journal of Systems Architecture: the EUROMICRO Journal - Defect and fault tolerance in VLSI Systems
Estimating the Economic Benefits of DFT
IEEE Design & Test
High Defect Coverage with Low-Power Test Sequences in a BIST Environment
IEEE Design & Test
High volume microprocessor test escapes, an analysis of defects our tests are missing
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Diagnosis and characterization of timing-related defects by time-dependent light emission
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Toward understanding "Iddq-only" fails
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Diagnosis method based on /spl Delta/Iddq probabilistic signatures: experimental results
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Replacing IDDQ Testing: With Variance Reduction
Journal of Electronic Testing: Theory and Applications
Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
10.1 Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
On the Comparison of IDDQ and IDDQ Testing
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Current Ratios: A Self-Scaling Technique for Production IDDQ Testing
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Universal Test Generation Using Fault Tuples
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Stuck-Fault Tests vs. Actual Defects
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An Empirical Study on the Effects of Test Type Ordering on
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Improving Delta-IDDQ-based test methods
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Improved Wafer-level Spatial Analysis for IDDQ Limit Setting
ITC '01 Proceedings of the 2001 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
APPLICATION AND ANALYSIS OF IDDQ DIAGNOSTIC SOFTWARE
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Current Signatures: Application
ITC '97 Proceedings of the 1997 IEEE International Test Conference
SO WHAT IS AN OPTIMAL TEST MIX? A DISCUSSION OF THE SEMATECH METHODS EXPERIMENT
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Current Signatures: Application
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A Study of Test Quality/Tester Scan Memory Trade-offs Using the SEMATECH Test Methods Data
ITC '99 Proceedings of the 1999 IEEE International Test Conference
ITC '99 Proceedings of the 1999 IEEE International Test Conference
An Histogram Based Procedure for Current Testing of Active Defects
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Current Ratios: A Self-Scaling Technique for Production IDDQ Testing
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Exploiting Defect Clustering to Screen Bare Die for Infant Mortality Failures: An Experimental Study
ITC '99 Proceedings of the 1999 IEEE International Test Conference
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Eliminating the Ouija® Board: Automatic Thresholds and Probabilistic IDDQ Diagnosis
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Towards Reducing "Functional Only" Fails for the UltraSPARCTM Microprocessors
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Journal of Electronic Testing: Theory and Applications
An Experimental Study of N-Detect Scan ATPG Patterns on a Processor
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
IDDX-based test methods: A survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Graphical IDDQ signatures reduce defect level and yield loss
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
On the Application of Dynamic Scan Chain Partitioning for Reducing Peak Shift Power
Journal of Electronic Testing: Theory and Applications
Estimation of fault-free leakage current using wafer-level spatial information
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper describes an experiment in which various semiconductor test methodologies (stuck-fault, functional, delay and IDDq) are applied to an ASIC device. The goal of this project is to provide the data that will enable manufacturers to optimize their application of the various tests. This project was supported through SEMATECH (Project S-121, "Semiconductor Test Method Evaluation ").