A novel algorithm to extract two-node bridges
Proceedings of the 37th Annual Design Automation Conference
Defect-Oriented Testing and Defective-Part-Level Prediction
IEEE Design & Test
An Experimental Chip to Evaluate Test Techniques: Experiment Results
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
On n-detection test sequences for synchronous sequential circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
13.3 Stuck-At Tuple-Detection: A Fault Model Based on Stuck-At Faults for Improved Defect Coverage
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experiment
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
A Scalable and Efficient Methodology to Extract Two Node Bridges from Large Industrial Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Stuck-Fault Tests vs. Actual Defects
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Experimental Evaluation of Scan Tests for Bridges
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Worst-Case and Average-Case Analysis of n-Detection Test Sets
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
N-detection under transparent-scan
Proceedings of the 42nd annual Design Automation Conference
Generation of broadside transition fault test sets that detect four-way bridging faults
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Multiple-detect ATPG based on physical neighborhoods
Proceedings of the 43rd annual Design Automation Conference
Forming N-detection test sets without test generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test vector chains for increased targeted and untargeted fault coverage
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Partitioned n-detection test generation
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Using stuck-at tests to form scan-based tests for transition faults in standard-scan circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Forward-looking reverse order fault simulation for n-detection test sets
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On clustering of undetectable single stuck-at faults and test quality in full-scan circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Generation of compact test sets with high defect coverage
Proceedings of the Conference on Design, Automation and Test in Europe
Non-uniform coverage by n-detection test sets
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-pattern n-detection stuck-at test sets for delay defect coverage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper studies the impact of N-detect scan ATPGpatterns on test quality and associated test costs. Anincremental method for test generation is presented.Metrics to evaluate the richness of the test set arepresented. The natural N-detect profiles of regular one-detecttest sets and the impact to test data volume and testtime of generating additional patterns is studied. Resultsare presented on an Intel® Pentium® 4 processor.Simulation results from evaluating the patterns on layoutextracted and random bridges are presented. Silicon datafrom production test shows the effectiveness of N-detecttests.