Defect-Oriented Testing and Defective-Part-Level Prediction
IEEE Design & Test
An Experimental Chip to Evaluate Test Techniques: Chip and Experiment Design
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
An Experimental Chip to Evaluate Test Techniques: Experiment Results
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
The Effect of Different Test Sets on Quality Level Prediction: When is 80% better than 90%?
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experiment
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Stuck-Fault Tests vs. Actual Defects
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults
Proceedings of the conference on Design, automation and test in Europe
On the decline of testing efficiency as fault coverage approaches 100%
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
An Experimental Study of N-Detect Scan ATPG Patterns on a Processor
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
A Measure of Quality for n-Detection Test Sets
IEEE Transactions on Computers
Worst-Case and Average-Case Analysis of n-Detection Test Sets
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Evaluation of the Quality of N-Detect Scan ATPG Patterns on a Processor
ITC '04 Proceedings of the International Test Conference on International Test Conference
Multiple-detect ATPG based on physical neighborhoods
Proceedings of the 43rd annual Design Automation Conference
Physically-aware N-detect test pattern selection
Proceedings of the conference on Design, automation and test in Europe
Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal of Electronic Testing: Theory and Applications
Defect aware X-filling for low-power scan testing
Proceedings of the Conference on Design, Automation and Test in Europe
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Multi-detect (N-detect) testing suffers from the drawback that its test length grows linearly with N. We present a new method to generate compact test sets that provide high defect coverage. The proposed technique makes judicious use of a new pattern-quality metric based on the concept of output deviations. We select the most effective patterns from a large N-detect pattern repository, and guarantee a small test set as well as complete stuck-at coverage. Simulation results for benchmark circuits show that with a compact, 1-detect stuck-at test set, the proposed method provides considerably higher transition-fault coverage and coverage ramp-up compared to another recently-published method. Moreover, in all cases, the proposed method either out-performs or is as effective as the competing approach in terms of bridging-fault coverage and the surrogate BCE+ metric. In many cases, higher transition-fault coverage is obtained than much larger N-detect test sets for several values of N. Finally, our results provide the insight that, instead of using N-detect testing with as large N as possible, it is more efficient to combine the output deviations metric with multi-detect testing to get high-quality, compact test sets.