An Experimental Chip to Evaluate Test Techniques: Experiment Results

Test methodologies and design automation for IBM ASICs

IBM Journal of Research and Development

A Cone-Based Genetic Optimization Procedure for Test Generation and Its Application to n$n$-Detections in Combinational Circuits

IEEE Transactions on Computers

Universal fault simulation using fault tuples

Proceedings of the 37th Annual Design Automation Conference

On Efficiently Producing Quality Tests forCustom Circuits in PowerPC™ Microprocessors

Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification

Definitions of the numbers of detections of target faults and their effectiveness in guiding test generation for high defect coverage

Proceedings of the conference on Design, automation and test in Europe

On identifying don't care inputs of test patterns for combinational circuits

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design

Defect-Oriented Testing and Defective-Part-Level Prediction

IEEE Design & Test

A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits Based on Partitioning and Reduction of a Precomputed Test Set

IEEE Transactions on Computers

Analysis of pattern-dependent and timing-dependent failures in an experimental test chip

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment

ITC '98 Proceedings of the 1998 IEEE International Test Conference

A highly testable and diagnosable fabrication process test chip

ITC '98 Proceedings of the 1998 IEEE International Test Conference

On test data compression and n-detection test sets

Proceedings of the 40th annual Design Automation Conference

Iddq Testing for High Performance CMOS - The Next Ten Years

EDTC '96 Proceedings of the 1996 European conference on Design and Test

On improving genetic optimization based test generation

EDTC '97 Proceedings of the 1997 European conference on Design and Test

A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference

On n-detection test sequences for synchronous sequential circuits

VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium

An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing

VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium

ATPG for scan chain latches and flip-flops

VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium

Bridges in sequential CMOS circuits: current-voltage signature

VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium

13.3 Stuck-At Tuple-Detection: A Fault Model Based on Stuck-At Faults for Improved Defect Coverage

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

6.3 Experimental Results for IDDQ and VLV Testing

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

On n-Detection Test Sets and Variable n-Detection Test Sets for Transition Faults

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium

REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experiment

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium

On the Evaluation of Arbitrary Defect Coverage of Test Sets

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium

Universal Test Generation Using Fault Tuples

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Deception by Design: Fooling Ourselves with Gate-level Models

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Test Method Evaluation Experiments & Data

ITC '00 Proceedings of the 2000 IEEE International Test Conference

A BIST Approach for Very Deep Sub-Micron (VDSM) Defects

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Comparing Functional and Structural Tests

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Identification of Defective CMOS Devices Using Correlation and Regression Analysis of Frequency Domain Transient Signal Data

ITC '97 Proceedings of the 1997 IEEE International Test Conference

BOARD LEVEL AUTOMATED FAULT INJECTION FOR FAULT COVERAGE AND DIAGNOSTIC EFFICIENCY

ITC '97 Proceedings of the 1997 IEEE International Test Conference

On Test Application Time and Defect Detection Capabilities of Test Sets for Scan Designs

ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors

A Comparison of Bridging Fault Simulation Methods

ITC '99 Proceedings of the 1999 IEEE International Test Conference

Resistive Bridge Fault Modeling, Simulation and Test Generation

ITC '99 Proceedings of the 1999 IEEE International Test Conference

Tradeoff Analysis For Producing High Quality Tests For Custom Circuits in PowerPCTM Microprocessors

ITC '99 Proceedings of the 1999 IEEE International Test Conference

1998 ITC Best Paper: Failure Analysis of Timing and IDDQ-only Failures from the SEMATECH Test Methods Experiment

ITC '99 Proceedings of the 1999 IEEE International Test Conference

Test Data Compression and Test Resource Partitioning for System-on-a-Chip Using Frequency-Directed Run-Length (FDR) Codes

IEEE Transactions on Computers

Balanced Excitation and Its Effect on the Fortuitous Detection of Dynamic Defects

Proceedings of the conference on Design, automation and test in Europe - Volume 2

An Experimental Study of N-Detect Scan ATPG Patterns on a Processor

VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium

Excitation, Observation, and ELF-MD: Optimization Criteria for High Quality Test Sets

VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium

ELF-Murphy Data on Defects and Test Sets

VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium

Estimating detection probability of interconnect opens using stuck-at tests

Proceedings of the 14th ACM Great Lakes symposium on VLSI

A Measure of Quality for n-Detection Test Sets

IEEE Transactions on Computers

Worst-Case and Average-Case Analysis of n-Detection Test Sets

Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Defect Aware Test Patterns

Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Detection probabilities of interconnect breaks: an analysis

Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI

N-detection under transparent-scan

Proceedings of the 42nd annual Design Automation Conference

Test chip experimental results on high-level structural test

ACM Transactions on Design Automation of Electronic Systems (TODAES)

On N-Detect Pattern Set Optimization

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design

Generation of broadside transition fault test sets that detect four-way bridging faults

Proceedings of the conference on Design, automation and test in Europe: Proceedings

X-masking during logic BIST and its impact on defect coverage

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Multiple-detect ATPG based on physical neighborhoods

Proceedings of the 43rd annual Design Automation Conference

Forming N-detection test sets without test generation

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Test data compression scheme based on variable-to-fixed-plus-variable-length coding

Journal of Systems Architecture: the EUROMICRO Journal

Test vector chains for increased targeted and untargeted fault coverage

Proceedings of the 2008 Asia and South Pacific Design Automation Conference

Resistive bridging fault simulation of industrial circuits

Proceedings of the conference on Design, automation and test in Europe

Physically-aware N-detect test pattern selection

Proceedings of the conference on Design, automation and test in Europe

Partitioned n-detection test generation

Proceedings of the 19th ACM Great Lakes symposium on VLSI

System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability

SUPERB: Simulator utilizing parallel evaluation of resistive bridges

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Forward-looking reverse order fault simulation for n-detection test sets

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Compacting test vector sets via strategic use of implications

Proceedings of the 2009 International Conference on Computer-Aided Design

Detection probabilities of interconnect breaks: an analysis

Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI

Improving the testability and reliability of sequential circuits with invariant logic

Proceedings of the 20th symposium on Great lakes symposium on VLSI

Post-silicon validation opportunities, challenges and recent advances

Proceedings of the 47th Design Automation Conference

On clustering of undetectable single stuck-at faults and test quality in full-scan circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Generation of compact test sets with high defect coverage

Proceedings of the Conference on Design, Automation and Test in Europe

Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns

Journal of Electronic Testing: Theory and Applications

A low overhead high test compression technique using pattern clustering with n-detection test support

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Test data compression based on geometric shapes

Computers and Electrical Engineering

Statistical defect-detection analysis of test sets using readily-available tester data

Proceedings of the International Conference on Computer-Aided Design

System-level impact of chip-level failure mechanisms and screens

Proceedings of the International Conference on Computer-Aided Design

Overcoming post-silicon validation challenges through quick error detection (QED)

Proceedings of the Conference on Design, Automation and Test in Europe

Non-uniform coverage by n-detection test sets

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Multi-pattern n-detection stuck-at test sets for delay defect coverage

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A Simulated Annealing Inspired Test Optimization Method for Enhanced Detection of Highly Critical Faults and Defects

Journal of Electronic Testing: Theory and Applications