Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Reliable computer systems (3rd ed.): design and evaluation
Reliable computer systems (3rd ed.): design and evaluation
A Mechanically Checked Proof of the AMD5K86TM Floating-Point Division Program
IEEE Transactions on Computers
Test Routines Based on Symbolic Logical Statements
Journal of the ACM (JACM)
Embedded Software-Based Self-Test for Programmable Core-Based Designs
IEEE Design & Test
An Experimental Chip to Evaluate Test Techniques: Experiment Results
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Debug methodology for the McKinley processor
Proceedings of the IEEE International Test Conference 2001
Reducing Test Application Time for Full Scan Embedded Cores
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
FRITS " A Microprocessor Functional BIST Method
ITC '02 Proceedings of the 2002 IEEE International Test Conference
X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Incorporating Ef.cient Assertion Checkers into Hardware Emulation
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Complementary use of runtime validation and model checking
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging
DSN '06 Proceedings of the International Conference on Dependable Systems and Networks
The good, the bad, and the ugly of silicon debug
Proceedings of the 43rd annual Design Automation Conference
A reconfigurable design-for-debug infrastructure for SoCs
Proceedings of the 43rd annual Design Automation Conference
Verification-guided soft error resilience
Proceedings of the conference on Design, automation and test in Europe
On the cusp of a validation wall
IEEE Design & Test
Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic
IEEE Transactions on Computers
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors
Proceedings of the 45th annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
25 Years of Model Checking
On Bypassing Blocking Bugs during Post-Silicon Validation
ETS '08 Proceedings of the 2008 13th European Test Symposium
BackSpace: formal analysis for post-silicon debug
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Boolean satisfiability from theoretical hardness to practical success
Communications of the ACM - A Blind Person's Interaction with Technology
Post-silicon bug localization for processors using IFRA
Communications of the ACM
Overcoming Early-Life Failure and Aging for Robust Systems
IEEE Design & Test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
VLSID '10 Proceedings of the 2010 23rd International Conference on VLSI Design
Post-silicon validation challenges: how EDA and academia can help
Proceedings of the 47th Design Automation Conference
BLoG: post-silicon bug localization in processors using bug localization graphs
Proceedings of the 47th Design Automation Conference
Scalable specification mining for verification and diagnosis
Proceedings of the 47th Design Automation Conference
Trace signal selection for visibility enhancement in post-silicon validation
Proceedings of the Conference on Design, Automation and Test in Europe
X-compact: an efficient response compaction technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Advances in simultaneous multithreading testcase generation methods
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
Threadmill: a post-silicon exerciser for multi-threaded processors
Proceedings of the 48th Design Automation Conference
Accelerating microprocessor silicon validation by exposing ISA diversity
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Quick detection of difficult bugs for effective post-silicon validation
Proceedings of the 49th Annual Design Automation Conference
Overcoming post-silicon validation challenges through quick error detection (QED)
Proceedings of the Conference on Design, Automation and Test in Europe
Deconfigurable microprocessor architectures for silicon debug acceleration
Proceedings of the 40th Annual International Symposium on Computer Architecture
Automatic concolic test generation with virtual prototypes for post-silicon validation
Proceedings of the International Conference on Computer-Aided Design
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Post-silicon validation is used to detect and fix bugs in integrated circuits and systems after manufacture. Due to sheer design complexity, it is nearly impossible to detect and fix all bugs before manufacture. Post-silicon validation is a major challenge for future systems. Today, it is largely viewed as an art with very few systematic solutions. As a result, post-silicon validation is an emerging research topic with several exciting opportunities for major innovations in electronic design automation. In this paper, we provide an overview of the post-silicon validation problem and how it differs from traditional pre-silicon verification and manufacturing testing. We also discuss major post-silicon validation challenges and recent advances.