Design for Debug: Catching Design Errors in Digital Chips
IEEE Design & Test
Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips
Journal of Electronic Testing: Theory and Applications
Are Our Design for Testability Features Fault Secure?
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Proceedings of the 1st conference on Computing frontiers
Automatic generation of breakpoint hardware for silicon debug
Proceedings of the 41st annual Design Automation Conference
Secure scan: a design-for-test architecture for crypto chips
Proceedings of the 42nd annual Design Automation Conference
Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test
IEEE Transactions on Computers
The good, the bad, and the ugly of silicon debug
Proceedings of the 43rd annual Design Automation Conference
Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?
IEEE Transactions on Computers
Securing Scan Control in Crypto Chips
Journal of Electronic Testing: Theory and Applications
Statistical diagnosis of unmodeled systematic timing effects
Proceedings of the 45th annual Design Automation Conference
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Interconnection fabric design for tracing signals in post-silicon validation
Proceedings of the 46th Annual Design Automation Conference
Post-silicon bug localization for processors using IFRA
Communications of the ACM
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A statistical diagnosis approach for analyzing design-silicon timing mismatch
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Post-silicon validation opportunities, challenges and recent advances
Proceedings of the 47th Design Automation Conference
BLoG: post-silicon bug localization in processors using bug localization graphs
Proceedings of the 47th Design Automation Conference
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Scan-based attacks on linear feedback shift register based stream ciphers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Embedded debug architecture for bypassing blocking bugs during post-silicon validation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
In-system and on-the-fly clock tuning mechanism to combat lifetime performance degradation
Proceedings of the International Conference on Computer-Aided Design
Accelerating microprocessor silicon validation by exposing ISA diversity
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Deconfigurable microprocessor architectures for silicon debug acceleration
Proceedings of the 40th Annual International Symposium on Computer Architecture
A failure prediction strategy for transistor aging
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Formal-analysis-based trace computation for post-silicon debug
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Built-in generation of multicycle functional broadside tests with observation points
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Clock Faults Induced Min and Max Delay Violations
Journal of Electronic Testing: Theory and Applications
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