microSPARCTM: A Case Study of Scan-Based Debug
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Structured Design-for-Debug - The SuperSPARCTM II Methodology and Implementation
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Test and debug strategy of the PNX8525 NexperiaTM digital video platform system chip
Proceedings of the IEEE International Test Conference 2001
Debug methodology for the McKinley processor
Proceedings of the IEEE International Test Conference 2001
Silicon Debug: Scan Chains Alone Are Not Enough
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Visibility enhancement for silicon debug
Proceedings of the 43rd annual Design Automation Conference
Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Interactive presentation: Low cost debug architecture using lossy compression for silicon debug
Proceedings of the conference on Design, automation and test in Europe
Online cache state dumping for processor debug
Proceedings of the 46th Annual Design Automation Conference
Real-time lossless compression for silicon debug
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Cache aware compression for processor debug support
Proceedings of the Conference on Design, Automation and Test in Europe
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Scan-based silicon debug is a technique that can be used to help find design errors in prototype silicon more quickly. One part of this technique involves the inclusion of breakpoint modules during the design stage of the chip. This paper focuses on an innovative approach to automatically generate breakpoint modules by means of a breakpoint description language. This language is illustrated using an example, and experimental results are presented that show the efficiency and effectiveness of this new method for generating breakpoint hardware.