MP3: The Definitive Guide
IC Failure Analysis: The Importance of Test and Diagnostics
IEEE Design & Test
FakeFault: a silicon debug software tool for microprocessor embedded memory arrays
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Using embedded infrastructure IP for SOC post-silicon verification
Proceedings of the 40th annual Design Automation Conference
The Manic Depression of Microprocessor Debug
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Core-Based Scan Architecture for Silicon Debug
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Automatic generation of breakpoint hardware for silicon debug
Proceedings of the 41st annual Design Automation Conference
Debug Support Strategy for Systems-on-Chips with Multiple Processor Cores
IEEE Transactions on Computers
Hardware Design Verification: Simulation and Formal Method-Based Approaches (Prentice Hall Modern Semiconductor Design Series)
Online cache state dumping for processor debug
Proceedings of the 46th Annual Design Automation Conference
Algorithms for state restoration and trace-signal selection for data acquisition in silicon debug
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Real-time lossless compression for silicon debug
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Cache aware compression for processor debug support
Proceedings of the Conference on Design, Automation and Test in Europe
Automated data analysis solutions to silicon debug
Proceedings of the Conference on Design, Automation and Test in Europe
A reverse-encoding-based on-chip bus tracer for efficient circular-buffer utilization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On signal tracing in post-silicon validation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
From RTL to silicon: the case for automated debug
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Embedded debug architecture for bypassing blocking bugs during post-silicon validation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An on-chip AHB bus tracer with real-time compression and dynamic multiresolution supports for SoC
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
X-tracer: a reconfigurable X-tolerant trace compressor for silicon debug
Proceedings of the 49th Annual Design Automation Conference
nuTAB-BackSpace: rewriting to normalize non-determinism in post-silicon debug traces
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The size of on-chip trace buffers used for at-speed silicon debug limits the observation window in any debug session. Whenever the debug experiment can be repeated, we propose a novel architecture for at-speed silicon debug that enables a methodology where the designer can iteratively zoom only in the intervals containing erroneous samples. When compared to increasing the size of the trace buffer, the proposed architecture has a small impact on silicon area, while significantly reducing the number of debug sessions.