Journal of Algorithms
A locally adaptive data compression scheme
Communications of the ACM
MP3: The Definitive Guide
IC Failure Analysis: The Importance of Test and Diagnostics
IEEE Design & Test
Design for Debug: Catching Design Errors in Digital Chips
IEEE Design & Test
Novel optical probing technique for flip chip packaged microprocessors
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Core-Based Scan Architecture for Silicon Debug
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Gbit/s lossless data compression hardware
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Automatic generation of breakpoint hardware for silicon debug
Proceedings of the 41st annual Design Automation Conference
Delay Fault Testing and Silicon Debug Using Scan Chains
ETS '04 Proceedings of the European Test Symposium, Ninth IEEE
CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging
DSN '06 Proceedings of the International Conference on Dependable Systems and Networks
Visibility enhancement for silicon debug
Proceedings of the 43rd annual Design Automation Conference
Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Hardware Design Verification: Simulation and Formal Method-Based Approaches (Prentice Hall Modern Semiconductor Design Series)
A lossless data compression and decompression algorithm and its hardware architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interactive presentation: Low cost debug architecture using lossy compression for silicon debug
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Post-silicon validation challenges: how EDA and academia can help
Proceedings of the 47th Design Automation Conference
Hardware-Based Load Value Trace Filtering for On-the-Fly Debugging
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Probabilistic Embedded Computing
Formal-analysis-based trace computation for post-silicon debug
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Silicon debug is becoming a key step in the implementation flow for the purpose of identifying and fixing design errors that have escaped pre-silicon verification. To address the lack of observability for the internal circuit nodes during silicon debug, embedded logic analysis enables real-time data acquisition from a limited number of internal signals. In this paper, we propose a novel architecture for embedded logic analysis that enables real-time lossless compression of debug data. To quantify the gain from using lossless compression in embedded logic analysis, we present a new compression-ratio metric that captures the trade-off between the area and the increase in the observation window. The proposed architecture is particularly suitable for in-field debugging on application boards, which have asynchronous events that inhibit the deterministic replay of debug experiments.