Islands of Synchronicity, a Design Methodology for SoC Design
Proceedings of the conference on Design, automation and test in Europe - Volume 3
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Transaction-Based Communication-Centric Debug
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Interactive presentation: Low cost debug architecture using lossy compression for silicon debug
Proceedings of the conference on Design, automation and test in Europe
A multi-core debug platform for NoC-based systems
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
In-band cross-trigger event transmission for transaction-based debug
Proceedings of the conference on Design, automation and test in Europe
Real-time lossless compression for silicon debug
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On-chip support for NoC-based SoC debugging
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A high-level debug environment for communication-centric debug
Proceedings of the Conference on Design, Automation and Test in Europe
Automated data analysis solutions to silicon debug
Proceedings of the Conference on Design, Automation and Test in Europe
On signal tracing in post-silicon validation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
From RTL to silicon: the case for automated debug
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Embedded debug architecture for bypassing blocking bugs during post-silicon validation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 50th Annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we present a core-based scan architecture for silicon debug, which is currently being standardized within Philips. The reasons behind the core-based debug architecture, together with implementation details, are described. The choices that were made during its development are explained using the experiences gained from two large Philips system chips that each utilize core-based design and test, and scan-based silicon debug. The results of an area-cost evaluation of the presented architecture for these two large system chips are also presented.